3D Memory Device Partial Program and Erase Operations
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Solution Overview
Problem
Three-dimensional memory devices face challenges in ensuring the reliability of program operations due to program disturbances that can lead to errors, particularly in lower memory cells, where channel areas are narrower and more susceptible to voltage influences.
Innovation Solution
The solution involves a method of performing partial program and erase operations in a sequential manner, starting from the uppermost memory cells and progressing downwards, with partial erase operations being conducted on non-programmed pages to initialize threshold voltages and prevent errors, using incremental step pulse and incremental step pulse erase methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If program operation is performed on vertically stacked memory cells in three-dimensional memory device, then integration density is improved, but program disturbances occur in lower memory cells causing reliability degradation
Solution Approach 1:
The patent divides the program operation into multiple segments: a first program operation on upper memory cells, followed by an erase operation on lower memory cells, and then a second program operation on the lower memory cells. This segmentation prevents program disturbances from affecting lower cells during the initial programming of upper cells, thereby resolving the reliability issue while maintaining high integration density through vertical stacking.
2Speed
If incremental step pulse program method is used, then program operation speed is improved, but program disturbances are generated affecting lower memory cells
Solution Approach 1:
The patent performs a preliminary program operation on upper memory cells before performing erase and program operations on lower memory cells. This preliminary action completes the programming of upper cells without causing disturbances to lower cells, as the lower cells are subsequently erased to remove any potential disturbances. This approach maintains fast program speeds while eliminating harmful program disturbances.
3Quantity of substance
If full program operation is performed on all pages, then data storage capacity is maximized, but operation time increases due to sequential processing requirement
Solution Approach 1:
The patent performs partial program operations on specific pages rather than sequentially processing all pages. By identifying and programming only the necessary pages (upper pages first, then lower pages after erase), the method achieves full data storage capacity while reducing total operation time compared to sequential full-page processing.
Data Source
AI summary
There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.