3D Semiconductor Memory Pass Transistor Gate Width Optimization
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Solution Overview
Problem
Current three-dimensional semiconductor memory devices face challenges in achieving enhanced electrical characteristics and reliability due to limitations in integration and signal transmission efficiency.
Innovation Solution
The design includes a three-dimensional semiconductor memory device with a cell string extending from a substrate, featuring first and second cell transistors connected to word lines, and pass transistors with varying effective gate widths to reduce time differences in signal transmission, along with a substrate structure that stacks word lines and select lines to optimize electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are designed with vertically stacked word lines to increase integration density, then integration density is improved, but signal transmission time difference between upper and lower word lines increases
Solution Approach 1:
The patent applies local quality by configuring pass transistors with different effective gate widths at different vertical positions. Specifically, pass transistors connected to upper word lines have larger effective gate widths than those connected to lower word lines, compensating for the increased transmission distance and capacitance load at upper levels of the three-dimensional structure.
Solution Approach 2:
The patent changes the parameter of effective gate width for pass transistors based on their vertical position. By adjusting the gate width parameter, the driving capability and signal transmission speed are optimized for each level, balancing the signal transmission time across the vertically stacked architecture.
2Productivity
If pass transistors with different effective gate widths are used to compensate for signal transmission time differences, then signal transmission efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the pass transistor network into multiple groups, with each group serving a specific vertical range of word lines. This segmentation allows for optimized signal transmission in each segment while reducing the overall complexity compared to individually customized transistors for every word line.
Solution Approach 2:
The patent systematically varies the effective gate width parameter of pass transistors according to their vertical position, creating a graduated structure that balances performance optimization with manufacturing feasibility.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.