3D Memory Passive Devices at Buried Source Line
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for forming passive devices in three-dimensional stacked memory structures are costly and require dedicated processing steps, making it challenging to integrate them efficiently within the architecture of high-density storage devices like 3D NAND memory devices.
Innovation Solution
A semiconductor structure is developed with passive devices, such as resistors and capacitors, formed at the buried source line level, utilizing a layer stack comprising patterned semiconductor and dielectric layers, and an alternating stack of insulating and electrically conductive layers, allowing for monolithic integration within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive devices are formed using dedicated processing steps in dedicated chip areas, then device functionality is achieved, but manufacturing cost increases and processing complexity increases
Solution Approach 1:
The patent merges the formation of passive devices with the existing memory stack structure fabrication process. The same alternating stack of insulating and conductive layers that forms the memory devices is also used to form the passive devices, eliminating the need for separate dedicated processing steps and chip areas for passive devices.
Solution Approach 2:
The alternating stack structure serves multiple functions: it forms both the active memory devices and the passive devices (capacitors, resistors, inductors). This multi-functional approach allows a single structure to fulfill multiple device requirements, reducing overall manufacturing complexity and cost.
2Area of stationary object
If passive devices are integrated at the buried source line level, then substrate area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The passive devices are nested within the same vertical stack structure as the memory devices. The alternating insulating and conductive layers are patterned to simultaneously define both memory stack structures and passive device structures, with the passive devices embedded at the buried source line level within the same fabrication sequence.
Solution Approach 2:
The patent utilizes the vertical dimension of the stacked structure to integrate passive devices at different levels (including the buried source line level) without increasing lateral substrate area. By stacking devices vertically and using selective patterning of the alternating layers, multiple device types are accommodated in the same footprint through three-dimensional arrangement.
3Reliability
If dedicated chip areas are used for passive devices, then device performance is maintained, but device density decreases
Solution Approach 1:
The patent transitions from two-dimensional lateral arrangement to three-dimensional vertical stacking, allowing passive devices to be integrated at multiple levels including the buried source line level. This vertical integration maintains device performance through proper structural design while dramatically increasing device density by utilizing the vertical dimension of the stacked architecture.
Data Source
AI summary
A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.