3D Memory Array Layout for Uniform Pattern Density
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Solution Overview
Problem
The existing methods for forming 3D memory devices face issues due to a large discrepancy in pattern density between areas with and without memory arrays, leading to process contamination and failure in subsequent processes.
Innovation Solution
Concurrently forming active and dummy memory arrays in adjacent areas on a substrate, using a stack of insulating and sacrificial layers, and etching trenches and holes to create conductive structures, followed by conformal deposition of metallic and semiconductor layers, thereby reducing process contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory arrays are formed only in specific areas of the substrate, then the actual memory device is created, but large discrepancy in pattern density occurs leading to process contamination
Solution Approach 1:
The patent creates dummy memory arrays that are copies of the actual memory array structure. These dummy arrays are formed in areas where no functional memory is needed, but they replicate the same pattern density and structural characteristics. This copying approach allows the fabrication process to proceed uniformly across the entire substrate without creating density discrepancies, thereby preventing process contamination while still producing the desired memory devices in the active areas.
Solution Approach 2:
The patent applies local quality by differentiating between active areas (where functional memory arrays are formed) and inactive areas (where dummy memory arrays are formed). The dummy arrays in inactive areas have the same local structural properties as the active arrays, ensuring uniform pattern density throughout the substrate. This local replication allows each area to have the appropriate quality needed for its function while maintaining overall process uniformity.
2Ease of manufacture
If pattern density varies significantly between different areas, then memory arrays can be formed in desired locations, but subsequent fabrication processes fail due to contamination
Solution Approach 1:
By creating dummy memory arrays that replicate the structure and pattern density of functional memory arrays, the patent enables flexible placement of memory arrays in desired locations while ensuring that all areas maintain consistent fabrication conditions. The dummy arrays serve as placeholders that preserve process reliability by preventing contamination during subsequent fabrication steps.
3Productivity
If the substrate is fully utilized with memory arrays, then production efficiency increases, but process contamination occurs due to density discrepancies
Solution Approach 1:
The patent achieves full substrate utilization by filling both active and inactive areas with memory array structures. The dummy arrays in inactive areas are copies of the functional arrays, ensuring uniform pattern density across the entire substrate. This approach maximizes productivity by utilizing 100% of the substrate area while preventing process contamination through maintained density uniformity.
Solution Approach 2:
The patent applies local quality by assigning different functional roles to different areas of the substrate while maintaining uniform structural properties. Active areas contain functional memory arrays, while inactive areas contain dummy memory arrays with identical local structure. This differentiation allows full substrate utilization for productivity while the uniform local quality prevents process contamination.
Data Source
AI summary
A semiconductor device includes a first and a second areas. The first area includes a plurality of first conductive stripes extending along a lateral direction and spaced from one another along a vertical direction, a first memory layer extending along the vertical direction, a first semiconductor layer extending along the vertical direction and coupled to a portion of the first memory layer, and second and third conductive stripes extending along the vertical direction, wherein the second and third conductive stripes are coupled to end portions of a sidewall of the first semiconductor layer. The second area includes a plurality of conductive sheets extending along the lateral direction and spaced from one another along the vertical direction, a second memory layer extending along the vertical direction and wrapped by the plurality of conductive sheets, and a second semiconductor layer extending along the vertical direction and wrapped by the second memory layer.