3D Memory Peripheral Circuit Bonding
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating peripheral circuits with support pillar arrays, leading to complexities in manufacturing and potential performance issues due to step height differences and process uniformity problems.
Innovation Solution
A three-dimensional memory device is designed with a first alternating stack of insulating and conductive layers, memory stack structures, and a contact-level dielectric layer, where a planar semiconductor material layer is bonded over a second alternating stack, and field effect transistors are formed on this layer to connect with the conductive layers, reducing step height differences and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If peripheral circuits are integrated with support pillar arrays in conventional three-dimensional memory devices, then device functionality is achieved, but manufacturing complexity increases and process uniformity deteriorates due to step height differences
Solution Approach 1:
The patent places peripheral circuits in a separate planar semiconductor layer bonded to the front surface, while support pillars remain in the bulk substrate. This spatial separation in different dimensions eliminates step height differences between memory arrays and peripheral circuits, thereby improving process uniformity during deposition and etching operations while maintaining full device functionality
Solution Approach 2:
The device is divided into two separate functional regions: memory array region with support pillars in the substrate, and peripheral circuit region in a bonded planar layer. This segmentation allows independent optimization of each region's manufacturing process, simplifying overall fabrication by eliminating the need to simultaneously process both regions through multiple high-aspect-ratio steps
2Adaptability or versatility
If peripheral circuits are integrated with support pillar arrays, then device functionality is achieved, but device complexity increases
Solution Approach 1:
By moving peripheral circuits to a separately bonded planar layer, the patent reduces structural complexity at the interface between memory arrays and peripheral circuits. The separate dimension allows simpler interconnect structures and eliminates the need for complex through-substrate vias and multi-level interlocking structures required in conventional integrated designs
Solution Approach 2:
The planar semiconductor layer acts as an intermediary carrier for peripheral circuits, physically decoupling them from the support pillar array while maintaining electrical connectivity through controlled interfaces. This intermediary structure simplifies the overall device architecture by providing a dedicated platform for peripheral circuits without complicating the memory array structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances process uniformity, reduces over-polishing errors, and simplifies the manufacturing process while enabling low aspect ratio, low resistance, and low capacitance electrical contacts between transistors and word lines, improving device performance and cost-effectiveness.
Implementation Method 1
bonding a planar semiconductor material layer to the contact-level dielectric layer
Data Source
AI summary
A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.