3D Memory Device with Peripheral Devices Under Dummy Dielectric Stack
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Solution Overview
Problem
Current three-dimensional NAND memory structures face challenges in achieving high device density and cost-effective manufacturing, particularly in forming efficient multilevel interconnect structures with multi-height electrically conductive via contacts.
Innovation Solution
The method involves forming a multilevel memory structure with an alternating stack of insulating and sacrificial material layers, where the sacrificial layers are selectively removed to create memory openings, and subsequently replaced with electrically conductive layers to form control gate electrodes, enabling the construction of high-density vertical NAND strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory structures are used, then manufacturing processes are simpler, but device density is low
Solution Approach 1:
The patent transitions from traditional planar (2D) memory structures to three-dimensional vertical NAND strings, stacking multiple insulating and conductive layers vertically to achieve high device density while managing structural complexity through systematic layering
Solution Approach 2:
The memory structure is divided into alternating insulating layers and conductive layers, with each layer serving specific functions. This segmentation allows for systematic fabrication and enables the vertical stacking architecture to achieve high density
2Quantity of substance
If multilevel interconnect structures with multi-height via contacts are implemented, then device density increases, but manufacturing complexity and cost increase
Solution Approach 1:
Dummy dielectric layer stacks are formed beforehand to define regions for peripheral devices before forming through-contact vias. This preliminary structuring simplifies subsequent via formation processes and enables efficient integration of peripheral circuits with the memory array
Solution Approach 2:
The alternating stack structure serves multiple functions: it provides the memory cell structure, defines interconnect levels, and creates regions for both array and peripheral devices. This multi-functionality reduces the need for separate structures and simplifies manufacturing
3Productivity
If peripheral devices are formed at higher elevations, then interconnect efficiency improves, but manufacturing steps increase
Solution Approach 1:
The formation of through-contact vias, peripheral device regions, and interconnect structures is merged into an integrated fabrication process. The dummy dielectric stacks serve as both structural elements and process guides, combining multiple functions into unified processing steps
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A method of manufacturing a structure includes forming an alternating stack of insulating layers (42) and spacer material layers (32) over a substrate (9), dividing the alternating stack into a first alternating stack (100, 300) and a second alternating stack (200), the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack (100), each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers (46) while leaving intact portions of the insulating layers (42) in the second alternating stack, and forming a contact via structure (84) through the second alternating stack to contact a peripheral semiconductor device under the second stack.