3D Memory Architecture with Peripheral Wafer Separation
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Solution Overview
Problem
Conventional planar semiconductor devices face challenges in scaling due to size limitations, leading to increased costs and complexity, while 3D memory devices offer a solution by stacking semiconductor wafers vertically to enhance density and performance, but require innovative methods for efficient interconnect formation and peripheral device integration.
Innovation Solution
A 3D memory device architecture is developed, featuring a first substrate with a semiconductor structure including a peripheral device and a doped semiconductor layer, where a memory array structure is formed between the doped layer and the semiconductor structure, with interconnection layers and through-silicon contacts facilitating electrical connections, and a memory controller for data storage and control operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor devices are scaled to smaller sizes, then device density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) semiconductor device architecture to three-dimensional (3D) stacked architecture. Multiple semiconductor wafers are stacked vertically with interconnect layers between them, enabling higher device density by utilizing the vertical dimension rather than continuing to scale lateral dimensions, thereby avoiding the manufacturing complexity and cost associated with further planar scaling.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate wafers that are stacked vertically. Each wafer can be manufactured independently using standard planar processes, and then bonded together with interconnect layers. This segmentation allows each wafer to be produced with existing mature technology while achieving higher overall density through vertical stacking.
2Quantity of substance
If 3D memory devices are formed by stacking semiconductor wafers, then device density is improved, but interconnect formation complexity increases
Solution Approach 1:
The patent forms interconnect structures, through-silicon vias, and contact holes in each wafer before the stacking process. This preliminary formation of interconnect pathways allows subsequent bonding to establish electrical connections between stacked wafers without requiring complex post-bonding interconnect formation, thereby reducing overall manufacturing complexity despite the 3D architecture.
Solution Approach 2:
The patent introduces interconnect layers as intermediary structures between stacked semiconductor wafers. These interconnect layers provide predefined pathways for electrical connections, simplifying the bonding process and reducing the complexity of forming vertical interconnects in the final 3D structure.
3Adaptability or versatility
If peripheral devices are integrated with memory array in 3D structure, then device functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent separates peripheral devices and memory array structures onto different wafers in the stack. This segmentation allows each wafer to be optimized and manufactured independently with appropriate process conditions, reducing the precision requirements compared to integrating all functions in a single wafer while still achieving full device functionality through vertical integration.
Solution Approach 2:
The patent uses multiple identical or similar wafer structures that are replicated and stacked. This copying approach allows standardization of interconnect patterns and bonding interfaces, reducing alignment precision requirements by using repeated, standardized geometries rather than unique, complex patterns.
Data Source
AI summary
A three-dimensional (3D) memory device includes a first substrate, a first semiconductor structure, and a second semiconductor structure. The first semiconductor structure is disposed on the first substrate. The first semiconductor structure includes a second substrate, and a peripheral device disposed over the second substrate, and the peripheral device is formed facing the first substrate. The second semiconductor structure is disposed on the first semiconductor structure. The second semiconductor structure includes a doped semiconductor layer, and a memory array structure disposed between the doped semiconductor layer and the first semiconductor structure.