3D Memory Stack With Post-Fabricated Peripheral Circuits
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Solution Overview
Problem
The challenge of increasing memory density in 3D memory is hindered by thermal degradation of peripheral circuit chips during high-temperature fabrication, limited material choices, and shrinking dimensions, which affect the reliability and performance of the memory chip.
Innovation Solution
The method involves fabricating peripheral circuit chips after forming the memory chip, allowing for the use of materials like copper interconnects and flexible process routes, and includes forming a semiconductor layer and contacts to connect the chips, with optional additional peripheral circuit layers, and a common source layer on the memory chip's backside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral circuit chip is fabricated before memory chip using existing techniques, then memory chip can be formed, but peripheral circuit chip suffers thermal degradation during high-temperature fabrication process
Solution Approach 1:
The patent inverts the conventional fabrication sequence by forming the memory chip first on the substrate, then forming the peripheral circuit chip on top of the memory chip. This inversion allows the memory chip to be fabricated at high temperatures first, followed by peripheral circuit fabrication at lower temperatures, thereby preventing thermal degradation of the peripheral circuit chip while maintaining high-temperature processing benefits for the memory chip.
2Adaptability or versatility
If peripheral circuit chip is fabricated before memory chip, then memory chip can be formed, but material selection for peripheral circuit chip is limited to adapt to memory chip processes
Solution Approach 1:
By inverting the fabrication sequence to form the memory chip first and then the peripheral circuit chip, the patent enables independent material selection for each component. The memory chip can use materials optimized for high-temperature processes, while the peripheral circuit chip can use materials like copper interconnects that would otherwise be incompatible with high-temperature memory fabrication processes.
3Quantity of substance
If number of levels in stack structure increases to improve memory density, then memory density increases, but lateral dimension of memory chip shrinks continuously
Solution Approach 1:
The patent addresses the lateral dimension shrinkage by extending the system into a third dimension - stacking the peripheral circuit chip on top of the memory chip. This vertical integration allows memory density to increase through additional stacking levels without further constraining the already-shrunken lateral dimensions of the memory chip, effectively trading lateral space for vertical space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and performance of peripheral circuit chips, improves memory density, and allows for further processing of the memory chip from the backside, supporting structures like gate induced drain leakage erase and backside pickup.
Implementation Method 1
performing ion implantation on the precursor to form a hydrogen-rich layer therein
Implementation Method 2
cleaving the precursor through the hydrogen-rich layer to leave the portion of the precursor below the hydrogen-rich layer on the connecting layer
Implementation Method 3
performing chemical mechanical polishing on the portion of the precursor below the hydrogen-rich layer to form the semiconductor layer
Implementation Method 4
after forming the common source layer, performing laser annealing on the common source layer
Data Source
AI summary
The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.