3D Non-Volatile Memory Device Peripheral Region Layout Optimization
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Solution Overview
Problem
In three-dimensional semiconductor devices, the increasing number of stacked word lines complicates the layout and increases the area of the peripheral region, making it difficult to efficiently couple word lines to transistors and global lines.
Innovation Solution
The solution involves forming transistors in the contact region of memory blocks, with an active region and isolation region alternately disposed, allowing conductive lines to extend across both, thereby simplifying the layout and reducing the peripheral region area by forming contact plugs between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stack number of word lines increases to enhance memory capacity, then the memory cell stacking density improves, but the layout complexity and peripheral region area increase
Solution Approach 1:
The device is divided into distinct functional regions: a cell region for memory cells and a contact region for transistors and global lines. This segmentation allows the memory cells to be stacked densely in the cell region while the peripheral components are concentrated in the contact region, thereby reducing overall layout complexity despite increased stacking density.
Solution Approach 2:
The invention transitions from a planar layout to a three-dimensional stacked structure. Memory cells are stacked vertically in the cell region, and conductive lines extend from the cell region through the isolation region to the contact region, utilizing the vertical dimension to increase storage capacity without proportionally increasing peripheral region area.
2Quantity of substance
If the stack number of word lines increases to enhance memory capacity, then the memory cell stacking density improves, but the peripheral region area increases
Solution Approach 1:
The contact region merges multiple functions: transistors are formed in the contact region, global lines are extended to the contact region, and contact plugs are formed in the contact region. This consolidation of peripheral components into a dedicated contact region reduces the overall peripheral region area compared to distributing these components across a larger perimeter.
Solution Approach 2:
By stacking memory cells vertically and extending conductive lines through the isolation region to reach the contact region, the invention utilizes the vertical dimension to increase capacity. This allows the peripheral region area to remain relatively constant while the memory cell stacking density increases.
3Ease of manufacture
If transistors are formed in the peripheral region using conventional techniques, then the word lines can be coupled to global lines, but the peripheral region area increases
Solution Approach 1:
Instead of forming transistors in the peripheral region as in conventional techniques, the invention inverts the approach by forming transistors in the contact region where memory blocks are stacked. This reversal allows the peripheral components to be integrated within the stacked structure, reducing the peripheral region area while maintaining coupling capability.
Solution Approach 2:
The contact region serves multiple functions: it houses transistors for coupling word lines to global lines, provides pathways for conductive lines to extend from the cell region, and contains contact plugs for electrical connections. This multi-functionality consolidates peripheral operations into a compact region.
Data Source
AI summary
A semiconductor device includes a substrate where a cell region and a contact region are defined, an isolation region and an active region disposed alternately in the contact region, transistors configured to include a gate formed over the substrate and a source and a drain formed in the active region at both sides of the gate, in the contact region, memory blocks configured to include conductive lines stacked over the substrate and formed over the transistors, the conductive lines being extended from the cell region to the contact region in the direction crossing over the isolation region and the active region, and contact plugs formed between the memory blocks in the contact region.