3D Memory Channel Phase Transition for Short-Channel Scaling
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in reducing contact resistance between the gate and channel material in three-dimensional memory devices, which affects driving capability and is exacerbated by the short channel effect as feature sizes shrink.
Innovation Solution
A method involving the formation of trenches with alternating conductive and dielectric layers, lining with a memory film, and filling with a second dielectric material, followed by crystallizing portions of the channel material using a thermal treatment to reduce electrical resistance and alleviate short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase memory density, then storage capacity is improved, but contact resistance between gate and channel material increases
Solution Approach 1:
The patent changes the physical state parameter of the channel material from amorphous to crystalline through thermal treatment. This parameter change reduces contact resistance at the gate-channel interface while maintaining the scaled-down feature sizes, thereby resolving the contradiction between high memory density and low contact resistance
Solution Approach 2:
The patent utilizes phase transition of the channel material from amorphous phase to crystalline phase through controlled thermal treatment. This phase transition fundamentally alters the electrical properties of the channel material, reducing contact resistance without requiring larger feature sizes, thus maintaining high memory density while improving electrical contact
2Quantity of substance
If feature sizes are reduced to increase memory density, then storage capacity is improved, but driving capability of transistors deteriorates
Solution Approach 1:
The patent changes the structural parameter of the channel material from amorphous to crystalline, which improves carrier mobility and reduces contact resistance. This enables transistors with smaller feature sizes to maintain adequate driving capability, resolving the contradiction between high memory density and sufficient transistor power
3Length of moving object
If feature sizes are reduced, then memory scaling is improved, but short channel effects are exacerbated
Solution Approach 1:
The patent changes the crystalline structure parameter of the channel material, which improves electrostatic control and reduces short channel effects. This allows continued scaling of feature sizes while maintaining device reliability, as the crystalline structure provides better carrier control in short channel geometries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and improves the driving capability of transistors by converting amorphous channel material to crystalline form, thereby enhancing the performance of three-dimensional memory devices.
Implementation Method 1
crystallizing first portions of the channel material after forming the SLs and BLs
Implementation Method 2
A method involving the formation of trenches with alternating conductive and dielectric layers, lining with a memory film, and filling with a second dielectric material, followed by crystallizing portions of the channel material using a thermal treatment
Data Source
AI summary
A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.