3D Semiconductor Memory Structure With Pillar-Supported Conductive Lines
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Solution Overview
Problem
3D NOR memory devices face challenges with strip collapse and wiggling due to narrow, tall gate films, leading to manufacturing yield issues and performance degradation from uneven channel layers and high resistance.
Innovation Solution
The formation of first dielectric pillars to support strips, replacement of dielectric layers with conductive lines, and formation of sacrificial layers to achieve flat sidewalls and uniform channel layers, improving manufacturing yield and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If narrow and tall gate films are used to increase memory density, then memory capacity increases, but strip collapse and wiggling occur leading to manufacturing yield degradation
Solution Approach 1:
The gate film structure is segmented into multiple thinner layers stacked vertically, replacing a single narrow and tall gate film. This segmentation reduces the aspect ratio of each individual gate film layer, preventing strip collapse and wiggling while maintaining the overall memory density through vertical stacking of multiple gate film segments.
Solution Approach 2:
The solution transitions from a single-dimensional narrow and tall gate film to a multi-dimensional stacked structure. By distributing the gate film functionality across multiple vertical layers, the patent achieves high memory density without requiring each individual layer to have a high aspect ratio, thus preventing structural collapse.
2Quantity of substance
If narrow and tall gate films are used, then memory density increases, but channel layers become uneven and resistance increases
Solution Approach 1:
The gate film is divided into multiple stacked layers, each with controlled thickness. This segmentation allows for better control of the channel layer formation process, as each gate film layer can be precisely deposited and controlled, resulting in more uniform channel layers without the distortion caused by narrow and tall single-layer structures.
3Ease of manufacture
If conventional 2D memory arrays are used, then manufacturing process is simpler, but memory density reaches scaling limits
Solution Approach 1:
The patent transitions from conventional 2D memory arrays to a 3D stacked architecture with multiple gate film layers stacked vertically. This dimensional change enables continued memory density scaling while maintaining manufacturing process compatibility with existing semiconductor fabrication techniques, effectively extending Moore's Law into the third dimension.
Data Source
AI summary
A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.