3D Memory Cell Layout Using Pillar Segmentation for Higher Density
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area of unit memory cells in two-dimensional structures, and existing three-dimensional designs face challenges in operational reliability.
Innovation Solution
A semiconductor device with a gate structure comprising alternately stacked conductive and insulating layers, channel structures, cutting structures, and slit structures that allow for increased memory cell density by separating pillar structures into first and second pillar structures, enhancing the number of memory cells without increasing the number of stacked conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are formed in a single layer over a substrate, then the manufacturing process is simple, but the integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional single-layer memory cell arrangement to three-dimensional stacked structure with multiple layers extending in the vertical direction. Multiple gate structures (first gate structure, second gate structure, third gate structure) are stacked above each other, with channel structures passing through them, thereby increasing integration density by utilizing the vertical dimension while maintaining manufacturability through systematic layer-by-layer fabrication processes
2Quantity of substance
If pillar structures are separated into first and second pillar structures by a cutting structure, then the number of memory cells increases, but the structural complexity increases
Solution Approach 1:
The patent divides each pillar structure into two separate pillar structures (first pillar structure and second pillar structure) by introducing a cutting structure that extends in the first direction. This segmentation allows each original pillar to serve as bit lines for different memory cells, effectively doubling the number of memory cells that can be formed with the same gate structures while maintaining a systematic and manageable structural organization
3Quantity of substance
If the number of stacked conductive layers is increased to increase memory cell density, then the integration density improves, but the manufacturing complexity and operational reliability challenges increase
Solution Approach 1:
Instead of simply increasing the number of stacked conductive layers, the patent segments the existing pillar structures using cutting structures that extend in the first direction. This segmentation approach increases memory cell density by creating additional bit line connections without proportionally increasing the number of stacked conductive layers, thereby reducing manufacturing complexity and improving operational reliability compared to approaches that rely solely on increasing stack height
Data Source
AI summary
A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.