3D Memory Cell Word Line Stack With Pillar Slits for Shorting Control
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Solution Overview
Problem
The miniaturization of memory cells in semiconductor devices leads to challenges in increasing net die yield due to structural limitations, making it difficult to reduce parasitic capacitance and improve capacitance.
Innovation Solution
A semiconductor device with vertically stacked word lines and pillar-shaped slits, incorporating etch stoppers and word line pads, which replace active layers to enhance word line resistance and prevent bridging or electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the memory cell is miniaturized, then the net die area is increased, but the parasitic capacitance increases and capacitance decreases
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertical stacking of word lines and memory structures. By stacking word lines vertically in multiple layers and creating pillar-shaped slits that extend through the stack, the invention achieves higher integration density in the vertical dimension while maintaining controlled parasitic capacitance through the pillar geometry that provides electrical isolation.
2Area of stationary object
If the size of the memory cell is miniaturized, then the net die area is increased, but the capacitance decreases
Solution Approach 1:
The patent implements vertical stacking of word lines and memory structures in the third dimension, allowing multiple memory cells to be stacked above each other. This three-dimensional arrangement increases the effective capacitance volume without increasing the planar footprint, thereby maintaining higher capacitance values while minimizing the net die area.
Solution Approach 2:
The patent creates a nested structure where pillar-shaped slits are formed within the vertically stacked word line structure. The pillars are positioned to extend through multiple word line layers, creating a hierarchical arrangement where isolation structures are nested within the memory stack, enabling compact integration while maintaining electrical isolation and capacitance.
3Productivity
If vertically stacked word lines are implemented, then memory cell integration is improved, but the risk of bridging and electrical shorting increases
Solution Approach 1:
The patent introduces pillar-shaped slits filled with dielectric material as intermediary structures between the vertically stacked word lines. These pillars act as physical barriers and electrical isolators that prevent direct contact between adjacent word lines, thereby preventing bridging and electrical shorting while allowing the vertical stacking architecture to achieve high integration density.
Solution Approach 2:
The patent segments the continuous word line structure by introducing discrete pillar-shaped isolation regions that divide and separate the word lines vertically. This segmentation creates distinct electrical zones between word lines, preventing unintended electrical coupling while maintaining the overall stacked architecture for high integration.
Data Source
AI summary
A semiconductor device includes: a word line stack disposed over a lower structure and including a plurality of word lines stacked in a direction vertical to a surface of the lower structure; and pillar-shaped slits penetrating edge parts of the word lines and including an etch stopper.