3D Memory Pillar Contact for Well Biasing
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in forming electrical contacts to doped well regions without occupying excessive area or interfering with device operation, particularly in achieving reliable biasing for NAND cells.
Innovation Solution
The implementation of monolithic three-dimensional memory devices with pillar-shaped support members featuring an electrically insulating outer material surrounding an electrically conductive core, which extends perpendicular to the substrate and contacts the doped well region, allowing for efficient electrical biasing and reduced noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrical contact structures are used to contact the doped well region, then electrical biasing can be achieved, but the area occupied is excessive and interference with device operation occurs
Solution Approach 1:
The patent transitions from planar contact structures to vertically extending pillar structures that contact the doped well region from above through the insulating layer. This vertical dimension allows electrical contact without occupying additional lateral area, resolving the contradiction between reliable electrical biasing and minimal area usage
Solution Approach 2:
The conductive core is nested within the insulating material to form a composite pillar structure. The insulating layer is then recessed to expose the conductive core, creating a nested configuration where the conductive element is embedded within the insulating matrix, enabling electrical contact while maintaining electrical isolation elsewhere
2Reliability
If larger contact structures are used to ensure electrical contact, then reliability improves, but noise interference increases
Solution Approach 1:
The insulating layer is formed as a thin film that is subsequently recessed to expose the conductive core. This thin film structure provides electrical isolation to minimize noise interference while the exposed conductive core ensures reliable electrical contact, resolving the contradiction between contact reliability and noise reduction
Solution Approach 2:
The insulating material acts as an intermediary between the conductive core and the surrounding environment. It provides electrical isolation that prevents noise interference while allowing the conductive core to maintain reliable electrical contact with the doped well region through controlled exposure
3Area of stationary object
If pillar-shaped support members with conductive cores are used, then area usage is minimized and noise interference is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the pillar structure: the conductive core provides electrical contact, the insulating material provides electrical isolation, and the combined structure serves as both a contact element and a support member. This integration reduces the number of separate components needed, offsetting the increased manufacturing complexity with functional consolidation
Solution Approach 2:
The pillar structure uses composite materials - a conductive core surrounded by insulating material - to achieve multiple functions simultaneously. The conductive core enables electrical contact while the insulating material prevents noise interference and provides structural definition, allowing area minimization without excessive complexity increase
Data Source
AI summary
A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.