3D Memory Word Line Decoding via Vertical Pillar Lines
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Solution Overview
Problem
Existing 3D memory arrays face challenges with the large number of word lines and bit lines requiring significant space for drivers, leading to increased die size and inefficiencies in decoding and accessing memory elements.
Innovation Solution
A 3D memory architecture with a vertical bit line architecture, where local and global bit lines are used in conjunction with segmented word lines, allowing for efficient decoding and reduced space requirements by using pillar lines to access memory elements across multiple planes, and employing select devices to switch pillar lines to global lines, thereby freeing up substrate space for other circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3D memory arrays use a large number of word lines and bit lines, then memory capacity increases, but die size increases and decoding efficiency decreases
Solution Approach 1:
The patent segments the bit line architecture into local bit lines (within each plane) and global bit lines (across multiple planes), connected via select devices. This segmentation allows efficient addressing of memory elements in 3D space without requiring a proportional increase in total line count, thereby maintaining high memory capacity while reducing die size.
Solution Approach 2:
The patent transitions from a 2D bit line architecture to a 3D architecture by introducing vertical pillar lines that extend through multiple planes. This dimensional change enables memory elements to be accessed across stacked planes using shared bit lines, increasing storage density without proportionally increasing the area occupied by decoding circuitry.
2Quantity of substance
If traditional 3D memory arrays use a large number of word lines and bit lines, then memory capacity increases, but decoding efficiency decreases
Solution Approach 1:
The patent segments the word lines into plane-specific word lines for each individual plane. This segmentation allows independent and parallel decoding of multiple planes simultaneously, improving decoding efficiency as memory capacity scales across multiple stacked planes without creating decoding bottlenecks.
Solution Approach 2:
By introducing the vertical dimension with pillar lines extending through multiple planes, the patent enables three-dimensional addressing schemes that can decode and access memory elements across stacked planes more efficiently than traditional two-dimensional architectures, thereby improving productivity without sacrificing capacity.
3Device complexity
If substrate space is occupied by drivers for word lines and bit lines, then decoding circuitry is complete, but space for other circuit elements is reduced
Solution Approach 1:
The patent merges the functions of local and global bit line drivers into shared decoding circuitry that operates across multiple planes. This consolidation reduces the total number of separate driver circuits required, completing the decoding functionality while minimizing the substrate area occupied by driver circuits, thereby freeing up space for other circuit elements.
Solution Approach 2:
The global bit lines serve multiple planes simultaneously, making them universal resources that reduce the need for plane-specific dedicated lines and drivers. This multi-functionality decreases the overall complexity and area requirement for decoding circuitry while maintaining complete addressing capability across all planes.
Data Source
AI summary
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines through the multiple layers of planes. The pillar lines are of a first type that act as local bit lines and a second type that provide access to the word lines by having respective memory elements preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.