3D Memory Cell Pillar Structure for Faster Low-Power Switching
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Solution Overview
Problem
Conventional memory device configurations face challenges in achieving high integration density, compact size, and improved performance due to processing conditions and design limitations, which impede reductions in size and enhance performance metrics such as faster memory cell switching speed and lower power consumption.
Innovation Solution
The development of a microelectronic device structure with a vertical memory array architecture that includes vertically stacked memory cells and conductive structures, allowing for improved integration density and performance by optimizing the configuration and performance of control logic devices through strategic material and structural design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory device configurations are used, then manufacturing processes are simplified, but integration density and device performance are limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory arrays to three-dimensional vertical memory arrays, stacking memory cells vertically to achieve higher integration density without proportionally increasing footprint area. This dimensional change allows more memory cells to be packed into the same device area while maintaining manufacturability through adapted fabrication processes.
Solution Approach 2:
The memory device is divided into multiple stacked decks, each containing tiers of memory cells separated by intermediate decks. This segmentation allows independent processing and optimization of each deck while achieving high overall integration density, resolving the conflict between complexity and precision by modularizing the structure.
2Manufacturing precision
If feature dimensions are reduced to increase density, then integration density improves, but manufacturing precision and performance deteriorate
Solution Approach 1:
Instead of continuously reducing lateral feature dimensions which degrades manufacturing precision, the patent stacks memory cells vertically in multiple decks. This allows maintaining larger, more manufacturable lateral dimensions while achieving high density through vertical multiplication of cell tiers across stacked decks.
Solution Approach 2:
Multiple decks are nested vertically, with each deck containing complete tiers of memory cells. This nesting approach allows scaling density by adding more nested levels rather than shrinking individual cell features, preserving manufacturing precision while increasing overall productivity and integration density.
3Productivity
If vertical memory array architecture is implemented, then integration density improves, but device complexity increases
Solution Approach 1:
The intermediate decks serve multiple functions: they separate and support multiple stacked memory cell decks, provide routing layers for electrical connections between tiers, and enable independent processing. This multi-functionality reduces overall structural complexity by consolidating support, separation, and interconnection functions into shared intermediate structures.
Solution Approach 2:
The vertical memory array is segmented into multiple independent decks that can be processed and assembled separately. Each deck is a self-contained unit with complete memory cell tiers, allowing modular fabrication and reducing the complexity of manufacturing the entire high-density structure in one process.
4Adaptability or versatility
If control logic devices are added to manage memory cells, then device functionality improves, but manufacturing precision and performance are limited by processing conditions
Solution Approach 1:
Control logic devices are merged with the memory array structure, with control logic tiers integrated into the same stacked deck architecture as memory cells. This integration allows control logic and memory cells to be fabricated using the same processing conditions and materials, optimizing performance while maintaining high manufacturing precision through unified fabrication processes.
Data Source
AI summary
A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.