3D Memory Cell Array Layout With Underlying Planar HV Transistors
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Solution Overview
Problem
There is a demand for higher performance and more compact memory architectures in integrated circuits, particularly in portable electronic devices, with a need for lower power consumption, faster read and write operations, and improved reliability, while also requiring efficient integration of memory solutions with host integrated circuits.
Innovation Solution
The integration of planar transistors with high band gap materials and metal-insulator-metal capacitors, along with a 1T-1C architecture, is employed to create a monolithic memory array that includes support circuitry beneath the memory cells, utilizing tungsten and copper metallization layers for efficient connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory architectures are used, then device footprint is larger, but integration density and compactness are reduced
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where memory cells are positioned vertically over planar transistors, transitioning from conventional two-dimensional planar integration to vertical stacking. This dimensional change enables higher integration density within a reduced footprint by utilizing the vertical dimension for memory cell placement while maintaining planar support circuitry at the base layer
Solution Approach 2:
The memory device is segmented into distinct functional layers: planar transistors form the support circuitry at the base, while memory cells are stacked vertically above. This segmentation allows independent optimization of each layer - planar transistors provide stable support functions with lower voltage requirements, while vertical memory cells achieve high density - without interference between functions
2Power
If higher voltage operations are implemented, then memory performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Different voltage regimes are assigned to different functional regions: planar transistors in the support circuitry operate at lower voltages suitable for control and read operations, while vertical memory cells tolerate and require higher voltages for write and erase operations. This local differentiation of operational characteristics allows each region to be optimized independently, reducing overall device complexity
Solution Approach 2:
The patent employs composite material structures in the vertical memory cells, including multi-layer dielectric stacks and conductive materials, enabling higher voltage operation through distributed voltage breakdown across multiple layers rather than requiring a single complex high-voltage transistor structure
3Ease of manufacture
If monolithic integration is used, then device cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The vertical stacking architecture separates lateral alignment requirements from vertical integration. Lateral alignment is simplified because planar transistors and memory cell footprints can be defined independently in the planar domain, while vertical integration is achieved through sequential deposition and etching processes that are more tolerant of lateral misalignment than conventional planar approaches
Data Source
AI summary
Memory device architectures including integrated high voltage planar transistor support circuitry underlying memory cell arrays are discussed related to improving density and device performance Such memory device architectures include planar transistors having wide band gap channel materials integrated with memory cell arrays using a number of metallization layers. The metallization layers between the planar transistors and the memory cells are predominantly tungsten and the metallization layers in which the memory cells are embedded are predominantly a metal other than tungsten.