3D Memory Conductive Plug Neck Structure for Low Contact Resistance
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face increased contact resistance due to impurities left in the surface layer of the substrate during slit etching, affecting the operational performance of the memory device.
Innovation Solution
A semiconductor structure and manufacturing method that utilize clean plasma to remove impurity doped regions in the substrate, reducing contact resistance by forming a conductive plug with a reduced neck structure and an enlarged bottom structure, which effectively decreases the impurity concentration and facilitates the formation of metal silicide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If slit etching is performed to create slits in the stacked structure, then the slits are successfully formed to divide channel pillars into groups, but impurities are left in the surface layer of the substrate which increases contact resistance
Solution Approach 1:
The patent extracts and removes the harmful impurities from the substrate surface layer using a cleaning process after slit etching. The cleaning step specifically targets and removes carbon-containing impurities that were deposited during the etching process, thereby reducing contact resistance without affecting the newly formed slit structure.
Solution Approach 2:
The patent applies a preliminary cleaning action before forming metal silicide on the substrate surface. By removing impurities from the surface layer before metal deposition, the contact interface is prepared in advance to ensure low contact resistance, preventing the harmful effect of impurity contamination.
2Productivity
If high aspect ratio slits (30-60) are formed with depth of 3-12 μm, then the slit structure is successfully created for device functionality, but the etching process deposits more impurities in the surface layer
Solution Approach 1:
The patent converts the harmful effect of impurity deposition during etching into a beneficial cleaning opportunity. By intentionally introducing a cleaning process step, the previously harmful impurity accumulation is transformed into a target for removal, and the cleaning process itself becomes a necessary part of the manufacturing sequence that enables subsequent low-resistance contacts.
Solution Approach 2:
The patent replaces the mechanical/physical etching process that deposits impurities with a chemical cleaning process using plasma. The plasma cleaning chemically reacts with and removes carbon-containing impurities, substituting a contaminating physical process with a purifying chemical process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces contact resistance between conductive plugs and the substrate, enhancing the operational performance of three-dimensional memory devices by effectively removing impurities using clean plasma etching.
Implementation Method 1
The plurality of impurity doped regions in the surface layer of the substrate are removed by clean plasma to form a bottom opening
Implementation Method 2
a metal silicide is formed on a surface of the substrate
Data Source
AI summary
A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.