3D Memory Polar Coder for Parallel Stages and Lower Latency
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Solution Overview
Problem
Existing polar coding technologies face inefficiencies in hardware usage and latency due to the reliance on two-dimensional memory structures, which limit the ability to fully exploit parallelism and increase memory bandwidth requirements, especially during decoding processes.
Innovation Solution
A polar coder architecture utilizing a logical three-dimensional memory structure allows for the processing of multiple stages concurrently, reducing memory requirements and enabling seamless data flow by alternating memory usage between columns, thereby enhancing hardware efficiency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory structures are used in polar coding, then the hardware implementation is simpler, but hardware efficiency decreases and memory bandwidth requirements increase
Solution Approach 1:
The patent transitions from traditional two-dimensional memory structures to a three-dimensional memory structure organized as a set of interleaved columns. This dimensional change enables more efficient memory utilization during polar coding operations, allowing simultaneous access to multiple stages across different columns and thereby improving hardware efficiency and reducing memory bandwidth requirements.
2Quantity of substance
If two-dimensional memory structures are used in polar coding, then the memory bandwidth requirement is reduced, but latency increases due to limited parallelism
Solution Approach 1:
By organizing memory in three dimensions with multiple interleaved columns, the system can perform parallel access operations across different columns simultaneously. This enables multiple stages of polar coding to be processed in parallel, significantly reducing latency while maintaining controlled memory bandwidth usage through efficient column-based data organization.
Solution Approach 2:
The memory is segmented into multiple interleaved columns that can be accessed independently and in parallel. This segmentation allows different stages of the polar coding process to be distributed across multiple memory columns, enabling simultaneous processing and thereby reducing overall latency.
3Adaptability or versatility
If flexible polar encoder kernels supporting various block sizes are implemented, then adaptability improves, but hardware efficiency decreases for short blocks due to unused hardware
Solution Approach 1:
The three-dimensional memory structure with interleaved columns enables the hardware to efficiently support variable block sizes by selectively activating only the necessary columns and stages for each specific block size. This prevents hardware waste by ensuring that only the required portion of the memory structure is utilized for each encoding operation.
Solution Approach 2:
The memory structure is designed to be dynamically configurable, allowing the active portion of the memory to be adjusted based on the input block size. This dynamic adaptation ensures that hardware resources are optimally utilized regardless of whether short or long blocks are being processed, maintaining high hardware efficiency across different block sizes.
Data Source
AI summary
A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2s<sub2>d</sub2>, where sd is a number of stages in a datapath of the one or more datapaths.