3D Memory Cell Stack With Low-Temperature Polysilicon Channels
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Solution Overview
Problem
The semiconductor industry faces challenges in 3D stacked chip integration due to the degradation of wiring performance and high power consumption, limited connectivity between layers, and the need for high-temperature processing that damages lower-temperature wiring layers, leading to low connectivity and defect density in current 3D stacked semiconductor chips.
Innovation Solution
The development of a 3D semiconductor device with a first single crystal layer and multiple metal layers, including interconnects and memory cells, where the top transistors are constructed using polysilicon channels and processed at temperatures below 400°C to avoid damaging lower layers, and the use of Atomic Layer Deposition (ALD) and optical annealing to repair defects and activate dopants without damaging metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed at high temperatures (>700°C) to achieve high performance, then transistor performance improves, but lower-temperature wiring layers (<400°C) are damaged
Solution Approach 1:
The patent divides the semiconductor structure into distinct temperature zones: a first semiconductor layer processed at high temperature for transistor formation, and a second semiconductor layer processed at low temperature for wiring formation. This segmentation allows each layer to be optimized for its specific temperature requirement without interfering with the other, resolving the contradiction between high-temperature transistor performance and low-temperature wiring integrity
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking, arranging transistor layers and wiring layers in different spatial dimensions. This allows high-temperature processed transistor layers and low-temperature processed wiring layers to coexist without thermal interference, as the wiring layers are positioned in a different spatial dimension below the transistor layers
2Speed
If 3D stacking is implemented to reduce wire lengths and improve connectivity, then wiring delay decreases, but manufacturing complexity and defect density increase
Solution Approach 1:
The patent performs preliminary processing of the first semiconductor layer (transistor layer) at high temperature before forming the second semiconductor layer (wiring layer). This preliminary action completes all high-temperature requirements upfront, allowing subsequent low-temperature wiring formation without risk of thermal damage, thereby simplifying the overall manufacturing process despite 3D stacking complexity
Solution Approach 2:
The patent changes the processing temperature parameter between layers: high temperature (>700°C) for the first semiconductor layer and low temperature (<400°C) for the second semiconductor layer. This parameter change enables 3D stacking with reduced manufacturing complexity, as each layer is processed under optimal conditions without requiring rework or repair of previously formed structures
3Adaptability or versatility
If connectivity between layers is increased to improve 3D stacking performance, then layer interconnection improves, but alignment precision and contact size requirements become more stringent
Solution Approach 1:
The patent utilizes vertical 3D stacking to increase connectivity between layers by forming multiple interconnection paths in the vertical dimension. This dimensional change allows high connectivity without proportionally increasing lateral alignment requirements, as connections are established through vertical vias and stacked layers rather than extensive lateral routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density connectivity and reliable operation of 3D stacked semiconductor chips with improved thermal management and reduced defect density, overcoming the limitations of current technologies by allowing for high-performance transistors and memory cells with increased connectivity and reduced thermal resistance.
Implementation Method 1
the use of Atomic Layer Deposition (ALD) and optical annealing to repair defects and activate dopants without damaging metal interconnects
Implementation Method 2
the use of Atomic Layer Deposition (ALD) and optical annealing to repair defects and activate dopants without damaging metal interconnects
Data Source
AI summary
A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.