3D Memory Device With Porous ILD Layers
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration densities due to the high cost and complexity of patterning processes, which restricts their performance and manufacturing efficiency.
Innovation Solution
A three-dimensional semiconductor memory device is developed with vertically arranged memory cell strings, incorporating a stack structure with interlayer dielectric layers that include pores, allowing for improved reliability and reduced parasitic capacitance through the use of low-k dielectric materials and varying pore distributions, thicknesses, and porosities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor memory devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cell structures. Multiple memory cell strings are arranged vertically with stack structures containing alternating ILD layers and gate electrodes, enabling higher integration density by utilizing the vertical dimension rather than only horizontal plane.
Solution Approach 2:
The patent employs composite interlayer dielectric structures with multiple ILD layers having different dielectric constants. Some ILD layers contain pores with low dielectric constants while others have higher dielectric constants, creating a composite structure that optimizes both electrical performance and structural integrity for high-density 3D integration.
2Reliability
If conventional ILD layers with high dielectric constant are used, then structural stability is maintained, but parasitic capacitance increases
Solution Approach 1:
The patent introduces porous interlayer dielectric layers containing pores filled with low-k dielectric material. These porous structures reduce the overall dielectric constant of the ILD layers, thereby decreasing parasitic capacitance between adjacent gate electrodes while maintaining adequate mechanical support and structural stability through the layered composite design.
Solution Approach 2:
The patent applies different dielectric constant values to different ILD layers based on their specific locations and functional requirements. Some ILD layers have lower dielectric constants to reduce parasitic capacitance in critical areas, while other layers maintain higher dielectric constants for structural support, creating localized optimization throughout the stack structure.
3Ease of manufacture
If uniform ILD layer thickness is used, then manufacturing is easier, but electrical performance varies
Solution Approach 1:
The patent employs ILD layers with varying thicknesses tailored to specific positional requirements within the stack structure. First ILD layers have different thicknesses compared to second ILD layers, with each thickness optimized for its location to achieve consistent electrical performance across different memory cell strings while remaining manufacturable through controlled deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D memory device enhances reliability and reduces parasitic capacitance, enabling higher integration densities and improved manufacturing efficiency while maintaining cost-effectiveness.
Implementation Method 1
at least one of the ILD layers including pores
Implementation Method 2
reduces parasitic capacitance through the use of low-k dielectric materials and varying pore distributions
Data Source
AI summary
Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.