3D Memory Device Probe Card Testing via Hybrid Bonded Interconnects
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Solution Overview
Problem
There is no effective method for testing the performance of internal structures of 3D memory devices using probe cards before packaging, which hinders the characterization and manufacturing yield of these devices.
Innovation Solution
A 3D memory device structure is developed with an interconnect layer and conductive pads at the backside for probe card testing, allowing for the evaluation of various characteristics and hybrid bonding quality, enabling testability and uniformity of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 3D memory device structure is developed with interconnect layer and conductive pads for probe card testing, then testability and manufacturing yield are improved, but device complexity increases
Solution Approach 1:
The 3D memory device is divided into separate functional modules including memory array structures, peripheral device structures, interconnect layers, and conductive pads. This segmentation allows independent testing of each module through probe cards before final packaging, improving manufacturing yield while managing complexity through modular design
Solution Approach 2:
Testing structures including conductive pads and interconnect layers are built into the device before packaging occurs. This preliminary action enables probe card testing to be performed on internal structures early in the manufacturing process, identifying defects before final assembly and improving overall yield
2Measurement precision
If hybrid bonding of peripheral and memory array structures is performed, then real device density testing is enabled, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture with multiple memory array structures bonded vertically. This dimensional change enables real device density testing by allowing probe cards to access internal structures through the bonded interface, providing accurate measurement of 3D memory characteristics
Solution Approach 2:
Interconnect layers and conductive pads serve as intermediary structures between the memory array structures and peripheral devices. These intermediaries enable electrical connections and signal transmission through the hybrid bonded interface, allowing testing equipment to access and characterize internal device structures
Data Source
AI summary
Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.