3D Memory Channel Structure With Protected Uniform Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional planar memory technologies face challenges in scaling and cost, necessitating a transition to three-dimensional memory architectures to enhance memory density.
Innovation Solution
A three-dimensional capacitor structure for memory devices is developed, involving the formation of an alternating dielectric stack on a substrate, with channel structures extending through the stack, and the use of a protection layer with non-uniform thickness to prevent over-etching and under-etching, ensuring uniform channel openings and improved data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then storage density is improved, but fabrication difficulty and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) memory architecture by stacking multiple memory layers vertically. This dimensional change allows continued density improvement without further lateral scaling, thereby avoiding the fabrication difficulties associated with sub-10nm planar processes. The vertical stacking of memory layers enables higher storage capacity while maintaining manufacturability at current technology nodes.
2Quantity of substance
If feature sizes approach lower limit, then storage density is improved, but manufacturing precision becomes challenging
Solution Approach 1:
By moving to 3D stacking, the patent achieves density improvement through vertical integration rather than lateral feature size reduction. This approach maintains manufacturing precision at current technology limits while achieving higher density. The uniform thickness requirement in the patent (5-20nm) represents a manageable precision target that can be achieved with existing deposition tools, avoiding the extreme precision challenges of sub-10nm planar features.
Solution Approach 2:
The patent specifies a controlled thickness range (5-20nm) for the dielectric layer protrusion, transforming the uncontrolled feature size problem into a controlled parameter optimization. By defining a practical thickness range rather than pushing to atomic-level precision, the patent achieves manufacturable precision while maintaining the 3D structure's electrical characteristics for high-density storage.
3Ease of manufacture
If etching process is performed to form channel openings, then channel structures are created, but over-etching or under-etching occurs causing non-uniform channels
Solution Approach 1:
The patent applies a protection layer to the sidewalls of the dielectric stack before performing the etching process. This preliminary protective action prevents lateral etching damage during the vertical etching operation, ensuring that the channel openings have uniform width and depth throughout the stacked structure. The protection layer acts as a barrier that maintains channel uniformity while allowing complete penetration through the alternating dielectric layers.
Solution Approach 2:
The protection layer serves as an intermediary element between the etching process and the dielectric stack sidewalls. It mediates the etching action by allowing vertical penetration while blocking lateral attack, thus controlling the etching process to produce uniform channels. This intermediary layer enables precise channel formation without direct contact between the etchant and the vulnerable sidewalls.
4Ease of manufacture
If dielectric layers are etched back to form recesses, then memory layers can be formed, but adjacent memory cells experience coupling
Solution Approach 1:
The patent creates recesses between adjacent memory cells by selectively etching back dielectric layers in specific regions. This segmentation isolates adjacent memory cells vertically, preventing electrical coupling and improving data retention. The recesses act as physical barriers that electrically separate neighboring storage elements while maintaining their individual functionality. This segmentation approach enables higher density by allowing closer spacing of memory cells without sacrificing reliability.
Data Source
AI summary
A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.