3D Memory Device Reducing Cell Area and Punch-Through via Vertical Stacking
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Solution Overview
Problem
Conventional planar NOR flash memory arrays face challenges in reducing bit size for high-density memory devices, leading to abnormal punch-through phenomena that affect electrical performance and data integrity due to shortened channel lengths.
Innovation Solution
A 3D memory device structure is developed with stacked layers, including epitaxial pillars, charge-trapping layers, high-k layers, and insulating layers, which reduces memory cell area and prevents punch-through by using a metal gate and high-quality insulating layers to improve electrical isolation and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length of memory cells is reduced to achieve higher density, then the area of memory cells is reduced, but the channel length is shortened causing abnormal punch through phenomenon
Solution Approach 1:
The patent transitions from a planar 2D memory structure to a 3D vertical structure by stacking multiple layers (first stacked structure and second stacked structure) above the substrate. This dimensional change allows memory cells to be arranged in three dimensions, achieving higher density without further reducing the already minimized planar area, thereby preventing punch-through effects that occur when channel length is excessively reduced.
Solution Approach 2:
The memory device is divided into multiple functional layers and stacked structures, with the channel region segmented into distinct zones (first channel region and second channel region) separated by different insulating layers. This segmentation allows independent optimization of each region, enabling the first channel region to maintain sufficient length for reliable operation while the overall structure achieves high density through vertical stacking.
2Area of moving object
If the channel length is shortened to reduce memory cell size, then the area is reduced, but punch through phenomenon occurs between drain and source regions
Solution Approach 1:
The patent introduces a first insulating layer positioned between the drain region and source region in the first channel region, and a second insulating layer in the second channel region. These intermediary insulating layers act as physical barriers that prevent charge carrier injection from the drain to the source, thereby eliminating the punch-through phenomenon while allowing the channel to maintain a shortened length for compact cell area.
Solution Approach 2:
By transitioning to a vertical 3D architecture with stacked structures, the patent achieves area reduction through the vertical dimension rather than further horizontal compression. This allows the horizontal channel length to be sufficient for preventing punch-through, while the overall cell footprint is minimized through multi-layer stacking.
3Productivity
If planar memory cell size is reduced by reducing gate length, then density increases, but electrical performance deteriorates due to punch through
Solution Approach 1:
The patent achieves high memory density by transitioning from planar to vertical stacking architecture, where multiple memory layers are stacked above the substrate. This dimensional transition allows density improvement without further reducing the already minimized planar cell area, thereby maintaining sufficient channel length for reliable electrical performance while achieving the required high density.
Solution Approach 2:
The memory device employs a composite structure combining multiple materials and layers including semiconductor layers, first and second insulating layers with different dielectric properties, conductive layers, and charge trapping layers. This composite architecture enables simultaneous optimization of density, electrical performance, and punch-through prevention by assigning different functional roles to each material layer.
Data Source
AI summary
A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.