3D Memory Word Line Layout for Uniform RC Loading
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Solution Overview
Problem
The integration level of two-dimensional memory devices is limited by the area occupied by unit memory cells and requires complex manufacturing equipment, restricting further enhancement in performance and storage capabilities.
Innovation Solution
A three-dimensional vertical semiconductor memory device with a stacked structure, featuring first and second stack regions, stair regions, and word lines and bit lines arranged in a vertical direction, along with sub-word line drivers connected through interconnect lines to uniform resistance-capacitance (RC) loading, allowing for enhanced integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory device structure is used, then manufacturing process is simpler, but integration level is limited
Solution Approach 1:
The patent transitions from a two-dimensional memory device structure to a three-dimensional vertical structure. The memory cells are arranged vertically with word lines extending in the vertical direction, bit lines arranged in multiple layers, and stacked capacitor structures, thereby increasing integration level without requiring more complex manufacturing equipment.
2Quantity of substance
If fine patterning technology is advanced to increase integration level, then unit memory cell area is reduced, but manufacturing equipment complexity increases
Solution Approach 1:
Instead of relying on advanced fine patterning to reduce unit cell area, the patent utilizes the vertical dimension to increase integration. The three-dimensional structure with vertically extending word lines and multi-layer bit lines allows higher density without requiring more complex patterning equipment.
Solution Approach 2:
The patent changes the structural parameters by introducing vertical stacking of memory cells, multi-layer bit line configurations, and vertically extending word lines. This parameter change from planar to vertical architecture increases integration level without depending on fine patterning capabilities.
3Reliability
If word lines are connected to multiple sub-word line drivers, then RC loading varies causing performance instability, but connecting to single driver reduces integration efficiency
Solution Approach 1:
The patent connects a first word line in a Kth layer and a second word line in an (N-K+1)th layer to the same sub-word line driver, creating symmetric RC loading conditions. This equipotential connection approach balances the resistance-capacitance product across all word line drivers, ensuring uniform signal transmission characteristics and stable performance while maintaining high integration efficiency.
Data Source
AI summary
A semiconductor memory device is provided. The device includes: first word lines in N layers, the first word lines extending from a first stack region toward first stair regions; second word lines in the N layers, the second word lines extending from a second stack region toward second stair regions; first memory cells provided in the first stack region; second memory cells provided in the second stack region; N first word line contacts connected to the first word lines in the first stair regions; and N second word line contacts connected to the second word lines in the second stair regions. A first word line in a Kth layer (K being an integer from 1 to N) among the first word lines and a second word line in an (N−K+1)th layer among the second word lines are commonly connected to one sub-word line driver.