3D Memory Word Line Pairing for Uniform RC Loading
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Solution Overview
Problem
The integration level of two-dimensional memory devices is limited by the area occupied by unit memory cells and requires complex manufacturing equipment, restricting further enhancement.
Innovation Solution
A three-dimensional vertical semiconductor memory device with a stair-like structure is designed, featuring first and second stack regions, word lines in multiple layers, bit lines, and sub-word line drivers connected through interconnect lines to uniformly distribute resistance-capacitance (RC) loading, allowing for enhanced integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory device structure is used, then manufacturing process is simpler, but integration level is limited and requires complex fine patterning equipment
Solution Approach 1:
The patent transitions from a two-dimensional memory device structure to a three-dimensional vertical structure. The memory cells are arranged vertically with word lines extending in the vertical direction, allowing integration level to increase without requiring finer lateral patterning. This dimensional change resolves the contradiction by enabling higher integration through vertical stacking rather than lateral miniaturization.
2Reliability
If word lines are connected to multiple sub-word line drivers, then RC loading is reduced, but device complexity increases
Solution Approach 1:
The patent combines symmetrically positioned word lines from different stack regions (first and second stack regions) to share common sub-word line drivers. Specifically, a first word line in a Kth layer and a second word line in an (N-K+1)th layer are commonly connected to one sub-word line driver. This merging approach reduces the total number of drivers needed while maintaining uniform RC loading through symmetric configuration.
Solution Approach 2:
The patent employs asymmetric indexing of word line layers (Kth layer and (N-K+1)th layer) to create symmetric pairing relationships. This asymmetric indexing scheme allows word lines at different vertical positions to be paired systematically, enabling balanced RC loading distribution across all drivers while reducing the total driver count through strategic symmetry exploitation.
Data Source
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AI summary
A semiconductor memory device is provided. The device includes: first word lines in N layers, the first word lines extending from a first stack region toward first stair regions; second word lines in the N layers, the second word lines extending from a second stack region toward second stair regions; first memory cells provided in the first stack region; second memory cells provided in the second stack region; N first word line contacts connected to the first word lines in the first stair regions; and N second word line contacts connected to the second word lines in the second stair regions. A first word line in a Kth layer (K being an integer from 1 to N) among the first word lines and a second word line in an (N-K+1)th layer among the second word lines are commonly connected to one sub-word line driver.