3D Memory Read Disturb Mitigation via Voltage Ramp Sequencing
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Solution Overview
Problem
Three-dimensional (3D) stacked memory devices, such as those using the Bit Cost Scalable (BiCS) architecture, face challenges with read disturb, particularly hot electron injection (HEI) type of read disturb, which occurs due to voltage gradients between word lines, leading to electron injection into charge trapping layers and increased threshold voltage of unselected memory cells.
Innovation Solution
The solution involves controlling the selected gate and word line voltages to minimize read disturb by ramping down SGD and SGS select gates before word lines, and adjusting voltage ramping to reduce capacitive coupling and channel gradients, thereby reducing electron injection and threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage gradients between word lines are utilized for sensing operations, then sensing capability is improved, but hot electron injection into charge trapping layers occurs causing read disturb
Solution Approach 1:
The patent applies preliminary action by ramping down the selected word line voltage before ramping down the selected SGD and SGS select gate voltages. This sequencing prevents the formation of voltage gradients that would cause hot electron injection during the sensing operation, thereby eliminating read disturb while maintaining sensing capability.
Solution Approach 2:
The patent changes the temporal parameters of voltage application by controlling the timing sequence of voltage ramping. Specifically, it modifies when voltages are applied and removed from different word lines and select gates, creating a voltage timing diagram that prevents harmful electron injection while preserving the necessary voltage gradients for sensing.
2Reliability
If electron injection into charge trapping layers is prevented, then read disturb is reduced, but threshold voltage stability may be affected
Solution Approach 1:
By ramping down the selected word line voltage before ramping down the select gate voltages, the patent preliminarily eliminates the condition that causes electron injection. This prevents threshold voltage shifts in unselected memory cells while maintaining proper threshold voltage stability in selected cells through controlled voltage sequencing.
3Object-affected harmful factors
If voltage ramping timing is adjusted to reduce capacitive coupling, then hot electron injection is minimized, but sensing operation complexity increases
Solution Approach 1:
The patent changes the temporal parameters of voltage application by implementing a specific ramping sequence. The selected word line voltage is ramped down first, followed by the selected SGD and SGS select gate voltages. This parameter change in timing reduces capacitive coupling and hot electron injection while maintaining manageable control complexity through systematic voltage sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces read disturb and maintains channel boosting, ensuring accurate data retention and programming efficiency in 3D memory devices.
Implementation Method 1
adjusting voltage ramping to reduce capacitive coupling and channel gradients
Implementation Method 2
hot electron injection (HEI) type of read disturb, which occurs due to voltage gradients between word lines, leading to electron injection into charge trapping layers
Data Source
AI summary
Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, the magnitude of a selected word line voltage is increased to be equal to pass voltages of unselected word lines, and the selected and unselected word line are ramped down at the same time, to avoid creating a channel gradient. In an example verify operation, the above procedure can be followed when the selected word line is at a source-side or middle range among all word lines. When the selected word line is at a drain-side among all word lines, a source-side select gate can be ramped down before the selected word line and a drain-side select gate can be ramped down after the selected word line.