3D Memory Read Disturb Reduction via Select Gate Transitions
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Solution Overview
Problem
Memory devices, particularly those with 3D stacked memory structures, face challenges in reducing read disturb, especially due to channel gradients and hot electron injection, which can increase the threshold voltage of memory cells, leading to data state disturbances.
Innovation Solution
Transitioning select gate transistors to a conductive state during the sensing process, particularly at the drain and source ends of unselected memory strings, helps in removing accumulated holes and reducing channel gradients, thereby minimizing read disturb by ensuring a faster decrease in channel potential when unselected word line voltages are ramped down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If select gate transistors are kept in non-conductive state during sensing, then power consumption is reduced, but channel gradients and hot electron injection increase causing read disturb
Solution Approach 1:
The select gate transistors are transitioned to conductive state periodically during the sensing process, specifically during voltage ramp-down phases of unselected word lines. This periodic activation allows hole removal and channel gradient reduction without requiring continuous conduction, thus balancing power consumption with read disturb reduction.
Solution Approach 2:
The select gate transistors act as an intermediary mechanism to control channel potential distribution. By strategically transitioning these transistors between conductive and non-conductive states, the system mediates between the conflicting requirements of power savings and read disturb prevention, using the transistor state changes to actively manage the channel environment.
2Productivity
If unselected word line voltages are ramped down quickly, then sensing speed is improved, but channel potential decrease is slower causing prolonged read disturb
Solution Approach 1:
The select gate transistors are transitioned to conductive state before the unselected word line voltages are ramped down. This preliminary action prepares the transistor to actively remove accumulated holes and reduce channel gradients during the voltage ramp-down process, ensuring faster channel potential decrease and shorter read disturb duration.
Solution Approach 2:
The system uses feedback from the sensing process to trigger select gate transistor transitions. When voltage ramp-down is detected or anticipated, the transistor state is changed accordingly to provide real-time compensation for channel gradient effects, dynamically adjusting the channel environment to maintain fast sensing while minimizing read disturb.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the duration of disturb-inducing channel gradients next to edge data memory cells, thereby minimizing read disturb and maintaining data integrity by ensuring a faster decrease in channel potential during the sensing process.
Implementation Method 1
read disturb, especially due to channel gradients and hot electron injection, which can increase the threshold voltage of memory cells
Implementation Method 2
One type of read disturb is caused by weak Fowler-Nordheim (F-N) tunneling due to a large voltage difference between the control gate and the channel of a cell
Implementation Method 3
The channel gradients results in electron-hole generation, where the holes can be accumulated in shallow traps in the channel adjacent to the select gate transistor
Data Source
AI summary
A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.