3D Nonvolatile Memory Read Method Reducing Disturbance
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Solution Overview
Problem
Three-dimensional (3D) semiconductor memory devices experience read disturbances due to different electrical parasitics compared to two-dimensional (2D) devices, requiring distinct driving methods, including different voltage levels and timing for read operations.
Innovation Solution
A method for performing read operations in nonvolatile memory devices with multiple cell strings, where specific turn-on and turn-off voltages are applied to string and ground selection transistors in a predetermined order and with predetermined levels to ensure uniform potential distribution across cell strings, reducing read disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read operations are applied to 3D semiconductor memory devices, then the read operation can be performed, but read disturbances occur due to different electrical parasitics compared to 2D devices
Solution Approach 1:
The patent applies different voltage levels and timing parameters for read operations in 3D semiconductor memory devices compared to 2D devices. Specifically, it uses distinct read voltages (e.g., Vread1, Vread2) and adjusts the timing of voltage application to account for the different electrical parasitics inherent in 3D structures, thereby reducing read disturbance while maintaining reliable read operations
Solution Approach 2:
The patent applies a first read voltage to unselected wordlines before applying the second read voltage to the selected wordline. This preliminary action prepares the electrical environment by establishing appropriate potential distributions in advance, which helps prevent read disturbance when the main read operation occurs on the selected memory cells
Data Source
AI summary
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.