3D Memory Read Scheme Reducing Power and Disturbance
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Solution Overview
Problem
As memory block size increases, power consumption and parasitic current leakage rise during memory operations in semiconductor memory devices, especially in 3D memory devices, due to the need to access a larger number of charge storage devices concurrently, leading to significant read disturbance and inefficiency.
Innovation Solution
Implementing a common region to data line read scheme, where all channels in a selected block are precharged from a common region, rendering unselected strings non-conductive through CG-to-channel capacitive coupling, reducing read disturbance and power consumption by allowing read current to flow from the common region to the data line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory block size is increased to improve storage capacity, then storage density is improved, but power consumption and parasitic current leakage increase during memory operations
Solution Approach 1:
The memory block is divided into multiple independent string groups, where each group can be selectively activated. Only the string group containing the target memory cell for the current operation is enabled, while other groups remain inactive. This segmentation allows large memory blocks to be physically divided into smaller operational units, reducing the number of concurrently active charge storage devices and thereby lowering power consumption and parasitic leakage during read, program, and verify operations.
2Quantity of substance
If memory block size is increased to improve storage capacity, then storage density is improved, but read disturbance to unselected strings increases
Solution Approach 1:
By dividing the memory block into separate string groups with independent control, the patent isolates the electrical effects of read operations to only the actively selected string group. The segmentation prevents voltage swings and capacitive coupling from affecting unselected strings in other groups, thereby eliminating read disturbance while maintaining large storage capacity through the combined size of all groups.
3Device complexity
If all-bit line architecture is used to simplify wiring, then device complexity is reduced, but current consumption and parasitic leakage increase
Solution Approach 1:
The all-bit line architecture is applied within each segmented string group rather than across the entire memory block. This allows the simplified wiring benefit to be realized locally in each group while the segmentation isolates the high current consumption and parasitic leakage to only the active group, preventing cumulative effects across the full memory block.
4Quantity of substance
If 3D memory structure is used to increase storage capacity, then storage density is improved, but the number of charge storage devices accessed concurrently increases leading to higher power consumption
Solution Approach 1:
The three-dimensional memory structure is divided into multiple string groups stacked vertically, where each group can be independently activated. During concurrent operations, only the specific vertical slice or group containing the target cells needs to be active, rather than activating all strings across the entire 3D block. This maintains the high storage density of 3D architecture while improving operational efficiency by limiting simultaneous access to a subset of charge storage devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach drastically reduces read disturbance and power consumption by minimizing the impact on unselected strings during memory operations, maintaining efficiency without increasing the number of high-voltage driver transistors, thus optimizing memory performance.
Implementation Method 1
rendering unselected strings non-conductive through CG-to-channel capacitive coupling
Implementation Method 2
allowing read current to flow from the common region to the data line
Data Source
AI summary
Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.