3D Memory Read-Out Circuit Parasitic Parameter Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The read-out time for three-dimensional memory is excessively long due to parasitic parameters and leakage currents affecting the reading speed and accuracy, leading to pseudo-reading phenomena.
Innovation Solution
A read-out circuit and method that includes a read reference circuit with bit line, transmission gate, and current mirror parasitic parameter matching modules, which generates a dynamic read reference current to counteract parasitic effects and leakage currents, allowing for accurate and fast signal reading by comparing the read current with the reference current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant reference current is used in the sensitive amplifier, then the circuit is simple to implement, but parasitic capacitance charging causes pseudo-reading and greatly restricts reading speed
Solution Approach 1:
The patent transforms the constant reference current into a dynamic reference current that varies over time. The reference current is designed to follow the charging curve of parasitic capacitance, with an initial large value that decreases over time. This dynamic adjustment allows the reference current to match the actual read current characteristics, eliminating pseudo-reading while improving reading speed.
Solution Approach 2:
The patent changes the parameter of reference current from constant to time-varying. By adjusting the reference current magnitude according to the parasitic capacitance charging process, the system adapts to the changing electrical conditions during reading, thereby resolving the contradiction between circuit simplicity and reading speed.
2Stability of the object's composition
If the reference current is maintained between reading high-resistance state current stable value and reading low-resistance state current stable value, then the reference current is stable, but pseudo-reading phenomenon is generated when parasitic capacitance is charged
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-setting the reference current waveform to match the expected parasitic capacitance charging curve. Before the actual reading operation, the reference current is configured to have the appropriate time-varying characteristics, ensuring that it accurately reflects the read current behavior from the beginning of the charging process, thus preventing pseudo-reading.
Solution Approach 2:
The patent implements feedback by designing the reference current to respond to the parasitic capacitance charging state. The reference current waveform is shaped based on the charging characteristics of parasitic capacitance, creating a feedback mechanism where the reference current automatically adjusts to match the actual electrical conditions in the memory array during reading.
3Quantity of substance
If three-dimensional memory structure is used to increase storage density, then storage capacity is improved, but parasitic devices in both vertical and planar directions increase the complexity and reading time
Solution Approach 1:
The patent introduces an intermediary element - the time-varying reference current - that mediates between the complex parasitic effects of three-dimensional memory and the reading operation. This reference current acts as a buffer that absorbs and compensates for the effects of parasitic capacitance and resistance, allowing the reading operation to proceed accurately despite the complex three-dimensional structure.
Data Source
AI summary
A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.