3D Memory Device With Recessed Dielectric Sidewalls
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Solution Overview
Problem
Current semiconductor memory technologies, such as volatile and non-volatile memories, face limitations in performance and efficiency due to the use of planar channel regions in thin film transistors (TFTs), which restrict the electric field strength and thus the write and read speeds of memory arrays.
Innovation Solution
The formation of three-dimensional channel regions in TFTs by recessing the sidewalls of dielectric layers to expose the top and bottom surfaces of word lines, allowing for the deposition of film stacks and the creation of bit and source lines, thereby enhancing the performance and efficiency of memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If planar channel regions are used in TFTs, then the device structure is simple and easy to manufacture, but the electric field strength is limited and write/read speeds are slow
Solution Approach 1:
The patent transitions from planar (2D) channel regions to three-dimensional channel regions by recessing dielectric layer sidewalls. This dimensional change increases the channel surface area and allows for stronger electric field confinement, directly improving write/read speeds while maintaining manufacturing feasibility through standard semiconductor processing techniques
2Force
If planar channel regions are used in TFTs, then the manufacturing process is simple, but the electric field strength is restricted
Solution Approach 1:
By creating three-dimensional channel regions through sidewall recessing, the patent increases the channel surface area and electric field confinement without adding complex manufacturing steps. The process uses standard recessing and deposition techniques to achieve stronger electric fields
3Productivity
If three-dimensional channel regions are formed by recessing dielectric layer sidewalls, then electric field strength increases and write speed improves, but the device structure becomes more complex
Solution Approach 1:
The patent uses three-dimensional channel regions formed by recessing dielectric layer sidewalls to increase electric field strength and improve write speed. This dimensional transition enhances performance while remaining compatible with standard semiconductor manufacturing processes
Data Source
AI summary
In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.