3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Current two-dimensional semiconductor memory devices face challenges in achieving high integration density and cost-effectiveness due to the need for expensive equipment for forming fine patterns, which limits their performance and manufacturing costs.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a semiconductor substrate with recessed regions, active patterns, insulating pillars, and select gates that increase integration density while reducing manufacturing costs, with the active patterns covering the recessed region surfaces and the insulating pillars filling the recessed areas, allowing for improved channel region control and threshold voltage adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar memory semiconductor devices are used, then the manufacturing process is simpler, but the integration degree is limited due to occupying area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked vertically with word lines extending horizontally through the stack, enabling significantly higher integration density by utilizing the vertical dimension rather than only the planar area.
2Manufacturing precision
If fine patterns are formed to increase integration degree, then the integration degree improves, but expensive equipment is necessary
Solution Approach 1:
By stacking memory cell layers vertically, the patent achieves high integration density without requiring extremely fine lateral patterning. The word lines are formed by patterning processes that define active regions, and multiple layers are stacked using standard fabrication techniques, avoiding the need for expensive equipment required for sub-10nm lateral patterning.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically. Each layer can be formed using standard patterning and deposition processes, and the layers are assembled through sequential fabrication steps, making the manufacturing process more accessible and cost-effective compared to forming ultra-fine single-layer patterns.
3Manufacturing precision
If three-dimensional memory cells are formed, then the area of semiconductor substrate is effectively utilized and integration degree increases, but the structure becomes more complex
Solution Approach 1:
The patent employs vertical stacking of memory cell layers with horizontal word lines extending through the stack. This configuration effectively utilizes the semiconductor substrate area by building upward in the vertical dimension, achieving high integration density while maintaining a structured and organized architecture that manages complexity through systematic layering.
4Reliability
If recessed regions are formed in the semiconductor substrate, then the electric field distortion is minimized and reliability improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent introduces recessed regions at specific locations in the semiconductor substrate where memory cell strings are formed. These localized recesses modify the electric field distribution in critical areas, reducing field distortion and improving device reliability. The recessed regions are selectively formed only where needed rather than throughout the entire substrate, balancing reliability improvement with manufacturing complexity.
Data Source
AI summary
In a three-dimensional semiconductor memory device, the device includes a semiconductor substrate having a recessed region, an active pattern extending in a direction transverse to the recessed region, an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region, and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate. The active pattern is disposed between the insulating pillar and the lower select gate.