3D Memory Device Using ReRAM to Reduce Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices face challenges in achieving high integration and operational reliability due to the need for precise lithography techniques and the use of MOSFETs in memory cells, which increases costs and complexity.
Innovation Solution
A memory device configuration using ReRAM with resistance change materials and select elements that allow for a three-dimensional matrix structure, eliminating the need for MOSFETs and reducing the size of select elements, enabling easier integration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFETs are used in memory cells, then operational reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the MOSFET component from the memory cell structure, replacing it with a direct resistance change material configuration. This eliminates the complex transistor gate structure, source/drain regions, and associated doping processes, thereby reducing device complexity while maintaining memory functionality through the resistance switching material alone.
Solution Approach 2:
The patent substitutes the mechanical/electrical control mechanism of MOSFETs (gate voltage control of channel conduction) with a materials-based resistance switching mechanism. The resistance change material directly modulates its electrical resistance in response to applied voltage, replacing the multi-component MOSFET system with a simpler material-based switching mechanism.
2Reliability
If MOSFETs are used in memory cells, then operational reliability is improved, but manufacturing cost increases
Solution Approach 1:
By removing the MOSFET structure, the patent eliminates multiple expensive manufacturing steps including photolithography for gate patterning, plasma etching for source/drain formation, and ion implantation for doping. The simplified structure requires fewer process steps and less expensive equipment, directly reducing manufacturing cost.
Solution Approach 2:
The patent changes the fundamental operating parameter from MOSFET voltage control to resistance switching. This parameter change enables the use of simpler deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) for forming the resistance change material layers, replacing complex semiconductor fabrication processes with more cost-effective thin-film deposition methods.
3Reliability
If conventional memory device integration is used, then operational reliability is maintained, but integration density decreases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to a three-dimensional stacked architecture. Multiple memory cell layers are vertically stacked and interconnected through through-silicon vias (TSVs) or contact holes, enabling significant increases in integration density by utilizing the vertical dimension while maintaining reliable operation through proven interconnect technologies.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked one on top of another, with each layer containing complete memory cell functionality. The layers are nested vertically with interconnect structures penetrating through multiple layers, creating a compact three-dimensional integration scheme that maximizes storage capacity per unit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration density, reduces power consumption, and improves operational reliability by allowing for lower voltage operations and reduced leakage current, while avoiding the need for negative voltage circuits.
Implementation Method 1
a resistance change material which transitions between a high resistance state and a low resistance state
Data Source
AI summary
A memory device includes a plurality of first interconnects extending in a first direction; a plurality of second interconnects extending in the first direction; a plurality of third interconnects extending in a third direction; and memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects, which surfaces are opposite to each other in the second direction. The resistance change layers are connected to the different second interconnects. A plurality of selectors connect the third interconnects to the first interconnects. One of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect. Gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.