3D Memory Array Using Resistive Isolation for Sneak Path Control
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Solution Overview
Problem
Current semiconductor storage arrays face challenges in efficiently accessing and managing multiple bits in a 3-D memory array due to the complexity of active components and high manufacturing costs, which limits their scalability and operational efficiency.
Innovation Solution
A 3-D memory array design utilizing resistive components instead of active components, with switching elements at the bottom of each post, allowing for independent access and analysis of individual row-planes, and employing conductive posts and rows to facilitate single-bit or multiple-bit accesses with precise voltage control to minimize sneak paths and ensure accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If active components are used to separate storage elements in a 3-D memory array, then switching and access control is achieved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent replaces active switching components (transistors) with passive resistive components to separate storage elements. This substitution eliminates the need for complex active switching mechanisms while maintaining the ability to control and access stored data through resistive isolation, thereby reducing device complexity and manufacturing cost.
Solution Approach 2:
The patent employs simple resistive components instead of expensive active components. These resistive separators are inexpensive, simple structures that provide adequate isolation functionality without requiring the complex fabrication processes needed for active devices, thus reducing overall manufacturing cost.
2Productivity
If multiple bits are accessed simultaneously in a 3-D memory array, then productivity increases, but sneak paths and current leakage increase
Solution Approach 1:
The patent applies resistive components locally between adjacent storage elements to provide targeted isolation. This localized resistive isolation prevents current from taking unintended paths (sneak paths) between non-selected storage elements, enabling multiple bits to be accessed simultaneously without excessive current leakage.
Solution Approach 2:
The resistive components act as intermediary elements between storage elements. These intermediaries provide controlled electrical isolation, allowing selective access to multiple storage elements while preventing unwanted current flow through non-selected elements, thus enabling parallel access with minimal sneak paths.
3Area of stationary object
If storage elements are stacked vertically above memory cell switches, then area utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory structure into distinct functional layers: memory cell switches in the substrate and storage elements stacked vertically above. This segmentation allows independent optimization of each layer and simplifies the manufacturing process by reducing the precision requirements for vertical alignment compared to fully integrated 3-D structures.
Solution Approach 2:
The patent transitions from a planar 2-D memory layout to a 3-D vertical stacking arrangement. By utilizing the vertical dimension (z-axis) for stacking storage elements above the substrate plane, the design achieves higher area utilization while maintaining manageable manufacturing precision requirements through the use of resistive separators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces manufacturing costs and enhances operational efficiency by allowing for low-cost, scalable 3-D memory arrays with improved bit access and reduced sneak paths, enabling accurate data reading and writing while maintaining low current leakage.
Implementation Method 1
These storage elements are stacked vertically above a memory cell switch in the substrate... a switching element can exist at the end of the column or more likely exists at the bottom of each post... Any one row-plane can be isolated from the rest and be accessed independently
Data Source
AI summary
The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be manufactured as a monolithic integrated circuit at low cost by virtue of the limited number of steps per layer of memory elements. The low number of steps results by having the storage elements separated by a resistive component as opposed to an active component. The 3-D array is in essence, an array of 2-D resistive arrays (row-planes) having a long dimension (typically along the rows) and a short dimension (typically in the direction of the stacked layers). Any one row-plane can be isolated from the rest and be accessed independently from all of the other row-planes in the 3-D array. This makes it possible to operate and analyze a single row-plane as a mostly stand-alone circuit. The present invention lends itself to single bit accesses as well as simultaneous multiple bit accesses.