3D Memory Resistor Structure Around Vertical Pillar Arrays
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Solution Overview
Problem
Current 3D memory technologies, such as NOR, NAND, and AND flash memory devices, face challenges in integrating resistors effectively around vertical pillar arrays, which are crucial for memory cell operations but often require complex and inefficient manufacturing processes.
Innovation Solution
The proposed semiconductor device and manufacturing method involve forming a resistor around a vertical pillar array by integrating a composite stack structure with a vertical pillar array and a resistor that extends through the composite stack structure, allowing for efficient integration with existing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional manufacturing processes are used to form resistors around vertical pillar arrays, then resistor integration is achieved, but the manufacturing process becomes complex and inefficient
Solution Approach 1:
The patent merges the resistor formation process with the existing composite stack structure fabrication by forming the resistor within the same trench structure that holds the vertical pillar array. This integration eliminates separate manufacturing steps and reduces overall process complexity while achieving effective resistor placement.
Solution Approach 2:
The composite stack structure serves multiple functions: it provides mechanical support for the vertical pillar array, acts as an insulating layer, and simultaneously houses the resistor structure. This multi-functionality reduces the number of separate components and simplifies the manufacturing process.
2Reliability
If resistors are integrated around vertical pillar arrays, then memory cell operations are enhanced, but manufacturing efficiency decreases
Solution Approach 1:
The resistor structure is formed preliminarily within the trench during the same fabrication sequence as the vertical pillar array, rather than adding it as a subsequent step. This preliminary integration maintains manufacturing efficiency while ensuring proper resistor placement for enhanced memory cell operations.
Solution Approach 2:
The resistor structure is nested within the composite stack structure trench, utilizing the same spatial envelope. This nesting approach allows both the vertical pillar array and resistor to coexist within a single structural framework, maintaining manufacturing efficiency while achieving functional enhancement.
Data Source
AI summary
A semiconductor device may be applicated in a three-dimensional AND flash memory device. The semiconductor device includes a dielectric substrate, a composite stack structure, a vertical pillar array and a resistor. The dielectric substrate includes a first region and a second region. The composite stack structure is located over the dielectric substrate in the first region and the second region. The vertical pillar array is disposed in the composite stack structure in the first region. The resistor is laterally adjacent to the vertical pillar array, extends below the composite stack structure in the second region, extends through the composite stack structure, and extends above the composite stack structure.