3D Memory Analog Resource Sharing for Asynchronous Multi-Plane Reads
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Solution Overview
Problem
Conventional 3D NAND memory devices face challenges in scaling planar memory cells due to process technology limitations and reliability issues, and existing asynchronous multi-plane independent read operations are inefficient due to high capacitive loading and resource duplication, leading to increased latency and power consumption.
Innovation Solution
A memory device with a first and second pump set configured to supply output voltages during steady and ramping phases, respectively, and linear regulators to generate voltage biases for different groups of word lines, utilizing a multiplexer circuit and controller to manage bidirectional switches for dynamic resource sharing across memory planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog resources are duplicated for each memory plane to support asynchronous multi-plane independent read operations, then read performance is improved, but device area and power consumption increase
Solution Approach 1:
The patent implements dynamic sharing of analog resources by introducing a controller that allocates pumps and linear regulators to different memory planes based on read operation requirements. The system transitions from static resource duplication to dynamic resource allocation, where resources are shared across multiple planes only when needed, reducing overall device area while maintaining asynchronous read capability.
Solution Approach 2:
The patent makes analog resources universal by designing pumps and linear regulators that can serve multiple memory planes rather than being dedicated to single planes. The controller enables these shared resources to be dynamically assigned to different planes performing read operations, achieving multi-functionality that reduces the total number of analog components required.
2Productivity
If analog resources are duplicated for each memory plane to support asynchronous multi-plane independent read operations, then read performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic sharing of analog resources by introducing a controller that allocates pumps and linear regulators to different memory planes based on read operation requirements. The system transitions from static resource duplication to dynamic resource allocation, where resources are shared across multiple planes only when needed, reducing overall device area while maintaining asynchronous read capability.
Solution Approach 2:
The patent makes analog resources universal by designing pumps and linear regulators that can serve multiple memory planes rather than being dedicated to single planes. The controller enables these shared resources to be dynamically assigned to different planes performing read operations, achieving multi-functionality that reduces the total number of analog components required.
3Quantity of substance
If shared word line is used across multiple memory planes to increase storage capacity, then storage density is improved, but capacitive loading increases during ramping operations
Solution Approach 1:
The patent segments the word line driving function by introducing separate first and second pump sets that can independently drive different groups of word lines. This segmentation allows selective activation of pump sets based on which memory planes are being accessed, reducing the total capacitive loading during ramping operations while maintaining high storage capacity through shared word lines.
Solution Approach 2:
The patent implements dynamic control of pump set activation through a controller that determines which pump set (first or second) should be activated based on the specific read operation requirements. This dynamic allocation reduces unnecessary capacitive loading by activating only the required pump set rather than all pumps simultaneously, while still supporting multiple memory planes with shared word lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the number of linear regulators and pumps, lowering area and power consumption while maintaining asynchronous multi-plane independent read performance, albeit with potential extra latency in certain command entry scenarios, and offers area and cost reductions.
Implementation Method 1
a first pump set coupled with the plurality of memory planes, and configured to supply a first output voltage to a plurality of linear regulators during a steady phase
Implementation Method 2
a second pump set coupled with the plurality of memory planes, and configured to supply a second output voltage to the plurality of linear regulators during a ramping phase
Implementation Method 3
a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines
Data Source
AI summary
A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.