3D Memory Array Ridge-Shaped Bit Line Contact Layout
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Solution Overview
Problem
The high manufacturing costs and complexity of 3D memory devices due to the large number of critical lithography steps required for each memory layer, which limits the scalability and cost-effectiveness of three-dimensional memory arrays.
Innovation Solution
A 3D memory device design featuring ridge-shaped semiconductor material strips separated by insulating material, with conductive lines arranged orthogonally and conformally over the stacks, forming interface regions where memory elements are integrated, reducing the need for critical lithography steps and allowing for a staircase-shaped structure that saves chip area and connects bit line contacts efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple planes of memory cells are stacked to achieve greater storage capacity, then memory density is improved, but the number of critical lithography steps increases manufacturing cost
Solution Approach 1:
The patent combines multiple memory layers into a single integrated 3D structure where semiconductor strips from different layers are interconnected through shared bit line contacts. This merging approach allows multiple memory planes to be manufactured simultaneously using the same lithography patterns, eliminating the need to multiply critical lithography steps by the number of layers while achieving high storage capacity
Solution Approach 2:
The patent transitions from planar 2D memory architecture to a 3D vertical architecture by stacking multiple semiconductor strips in the vertical dimension. This dimensional change enables increased storage capacity without proportionally increasing the lithography complexity, as the vertical stacking is achieved through conformal deposition and shared contact structures rather than additional lateral lithography steps
2Quantity of substance
If memory cells and interconnects are densely packed to increase density, then storage capacity is improved, but chip area footprint increases
Solution Approach 1:
The patent achieves high memory cell density by utilizing the vertical dimension through stacked semiconductor strips arranged in multiple layers. This 3D configuration allows numerous memory cells to be packed within a small lateral footprint, as the density increase comes from vertical stacking rather than lateral expansion of the chip area
3Adaptability or versatility
If the number of control gates is increased to improve memory functionality, then memory performance is improved, but manufacturing complexity increases due to additional critical lithography steps
Solution Approach 1:
The patent implements multi-functional control gates that serve multiple purposes across different memory layers. The same control gate structure is used universally for selecting and controlling memory cells in multiple stacked layers, eliminating the need for separate critical lithography steps for each layer's control gates while maintaining full memory functionality and adaptability
Data Source
AI summary
A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.