3D Memory Ridge Stacks for High Density and Low Cost
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Solution Overview
Problem
The high manufacturing costs and complexity of three-dimensional (3D) memory devices due to numerous critical lithography steps required for each memory layer, limiting the scalability and cost-effectiveness of 3D memory technologies.
Innovation Solution
The 3D memory device architecture features ridge-shaped stacks of semiconductor material with conformal word lines and memory elements at cross-points, allowing for self-aligned formation of memory cells with reduced alignment steps and improved pitch, enabling a higher density memory array with lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers of memory cells are stacked to achieve greater storage capacity, then storage density is improved, but the number of critical lithography steps increases, leading to higher manufacturing costs
Solution Approach 1:
The memory device is divided into multiple independent memory layers, each with its own bit lines and control gates. This segmentation allows each layer to be formed using separate lithography steps, but the overall structure achieves high density through vertical stacking. The patent describes 'a first plurality of bit lines... a second plurality of bit lines' and 'first memory layer... second memory layer' that are spatially separated and independently controllable.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical stacking by adding the vertical dimension. Multiple memory layers are stacked above each other, with bit lines extending through insulating layers to connect to different memory layers. This dimensional change allows exponential growth in storage capacity without proportionally increasing lithography complexity, as the same lithography processes are applied repeatedly in the vertical direction.
2Quantity of substance
If more control gates are layered vertically to increase memory density, then storage capacity improves, but the conductivity of the vertical channel and program/erase processes become limiting factors
Solution Approach 1:
The patent applies different material compositions and structural configurations to different regions of the vertical channel to optimize local electrical properties. The channel region contains 'a first doped region... a second doped region' with different doping types and concentrations, creating locally optimized conductivity zones that maintain reliable electron transport even as the number of vertical control gates increases.
Solution Approach 2:
The vertical channel structure employs composite materials including semiconductor material, doped regions, insulating materials, and conductive materials in a multi-layered configuration. This composite structure allows simultaneous optimization of electrical conductivity, insulation between gates, and mechanical stability, enabling reliable operation with multiple vertical control gates.
3Ease of manufacture
If critical lithography steps are reduced to lower manufacturing costs, then ease of manufacture improves, but memory element size and alignment precision may be compromised
Solution Approach 1:
The patent implements self-aligned fabrication processes where certain structural features automatically align with each other without requiring additional critical lithography steps. For example, the vertical channel structures and control gates are formed using processes that inherently maintain alignment, reducing the need for high-precision lithography while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary structural formation steps that establish alignment references before subsequent lithography processes. By pre-forming vertical channels, insulating layers, and conductive regions in specific configurations, the patent creates a framework that guides subsequent material deposition and patterning, thereby reducing the precision requirements for later lithography steps.
Data Source
AI summary
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.