3D Memory Array Self-Aligned Ridge Stacks
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Solution Overview
Problem
High manufacturing costs and complexity in producing three-dimensional memory devices due to the large number of critical lithography steps required for each memory layer, limiting the scalability and cost-effectiveness of existing 3D memory technologies.
Innovation Solution
A 3D memory device structure featuring ridge-shaped stacks of conductive material separated by insulating material, with conductive lines extending orthogonally and conformally over the stacks, allowing for self-aligned memory cell formation using a single etch mask and reducing the need for critical alignment steps, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple critical lithography steps are used for each memory layer, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The conductive lines are formed to have surfaces that conform to the surface of the stacks, creating a self-aligned structure where the memory elements are automatically positioned at the correct locations at cross-points between conductive strips and conductive lines, eliminating the need for separate alignment steps
Solution Approach 2:
The patent transitions from planar 2D memory architecture to a 3D vertical architecture with stacks extending in the vertical direction, allowing memory cells to be formed at multiple levels and cross-points, thereby increasing storage density without proportionally increasing lithography complexity
2Manufacturing precision
If multiple critical lithography steps are used for each memory layer, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The conformal configuration of conductive lines over stacks creates self-aligned memory elements, eliminating the need for multiple costly critical lithography steps and reducing manufacturing complexity while maintaining precision
Solution Approach 2:
The patent combines multiple functions into the conformal deposition process, where the same process that forms the conductive lines also simultaneously defines the memory element positions, reducing the total number of manufacturing steps and costs
3Quantity of substance
If 3D array structure is implemented, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements a 3D array structure with stacks of conductive strips separated by insulating material, with conductive lines extending orthogonally over the stacks, creating memory elements at cross-points in three dimensions, thereby achieving high storage capacity
Solution Approach 2:
The self-aligned configuration where conductive line surfaces conform to stack surfaces automatically positions memory elements at correct 3D cross-points, eliminating the need for multiple alignment steps and reducing manufacturing complexity despite the increased dimensional complexity
Data Source
AI summary
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.