3D Memory Architecture With Ridge Stacks And Orthogonal Word Lines
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Solution Overview
Problem
The high manufacturing costs associated with three-dimensional (3D) memory devices due to the numerous critical lithography steps required for each memory layer, which limits the use of 3D arrays despite their potential for higher storage density and lower costs per bit.
Innovation Solution
A memory device architecture featuring ridge-shaped stacks of semiconductor material strips separated by insulating material, with word lines arranged orthogonally to form a 3D array of memory cells at cross-points, utilizing a single etch mask for alignment and conformal deposition to reduce manufacturing complexity and costs, and incorporating diodes for selection and programming of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers of memory cells are stacked to achieve greater storage capacity, then storage density is improved, but the number of critical lithography steps increases, leading to higher manufacturing costs
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional 3D memory architecture by stacking multiple planes of memory cells vertically. This dimensional change enables greater storage capacity within the same footprint while the self-aligned formation process addresses the manufacturing complexity issue by eliminating the need for additional critical lithography steps that would normally be required for each stacked layer.
Solution Approach 2:
The patent combines multiple memory cell planes into a single integrated 3D structure where word lines and bit lines from different planes are merged into shared conductive layers. This merging approach allows multiple layers to be formed simultaneously through a single lithography process, thereby increasing storage capacity without proportionally increasing the number of critical lithography steps.
2Quantity of substance
If more control gates are added to increase memory density, then storage capacity is improved, but the conductivity of the vertical channel deteriorates, limiting further scaling
Solution Approach 1:
The patent segments the memory structure into discrete planes separated by isolation layers, with each plane having its own set of control gates. This segmentation allows independent optimization of each plane's conductivity characteristics while maintaining high overall memory density. The vertical channel is divided into segments that can be independently controlled, preventing the degradation of conductivity that would occur with a continuous long channel.
Solution Approach 2:
The patent applies different material compositions and doping profiles to different regions of the vertical channel to optimize local conductivity. By tailoring the electrical properties of specific channel segments near control gates versus other regions, the patent maintains high conductivity where needed while still achieving high memory density through multiple controlled gates.
Data Source
AI summary
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.