3D Memory Device Ridge Stacks Word Line Contact Reduction
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Solution Overview
Problem
Current 3D memory devices face challenges in increasing memory density without compromising process window and yield, and are limited by the need for multiple word lines contacts, which can increase production costs and device size.
Innovation Solution
A 3D memory device structure featuring multi-layer stacks with ridge stacks and U-shaped memory cell strings, reducing the number of word lines contacts by connecting memory cells in series across different ridge stacks, allowing fewer contacts to be used while maintaining memory density and improving fabrication yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines contacts is increased to accommodate higher memory density, then memory density is improved, but device complexity and production cost increase
Solution Approach 1:
The patent merges multiple word line contacts into fewer contacts by redistributing and sharing contacts across multiple conductive strips and memory cell strings. Specifically, a reduced number of word line contacts are used to connect to multiple conductive strips through shared connections, thereby reducing overall device complexity while maintaining high memory density.
Solution Approach 2:
Each word line contact is designed to serve multiple functions by connecting to multiple conductive strips and memory cell strings simultaneously. This multi-functional design allows a single contact to control multiple word lines across different memory cell arrays, reducing the total number of contacts needed while increasing memory density.
2Quantity of substance
If the pitch of word lines is shrunk to accommodate more word lines contacts, then memory density is improved, but manufacturing precision and reliability deteriorate due to oxide breakdown
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of word lines to a three-dimensional vertical architecture where conductive strips are stacked in multiple layers. This dimensional change allows memory density to increase vertically rather than requiring further shrinkage of horizontal pitch, thereby maintaining adequate process windows and avoiding oxide breakdown issues.
3Quantity of substance
If the physical size of the device is increased to accommodate more word lines contacts, then memory density is improved, but device compactness deteriorates
Solution Approach 1:
The patent employs vertical stacking of conductive strips and memory cell strings in the third dimension, allowing memory density to increase without proportionally increasing the device footprint. This 3D architecture enables high memory density while maintaining device compactness and portability.
Solution Approach 2:
The patent implements a nested structure where multiple conductive strips and memory cell strings are vertically stacked and integrated within a compact footprint. The multi-layer stack configuration allows memory cells to be nested in three-dimensional space, achieving high density without increasing device area.
Data Source
AI summary
A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.