3D Memory Sense Amplifier Layout for Congestion-Free Routing
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Solution Overview
Problem
Three-dimensional memory devices, such as 3D DRAM devices, face complex and congested routing designs for connecting DRAM cells to control logic circuitry, which affects performance.
Innovation Solution
The implementation of an open architecture with vertically offset control logic circuitry, including sense amplifiers and sub-word line drivers, that facilitates efficient electrical connections through digit and word lines, reducing routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic circuitry is integrated within a base control logic structure underlying a memory array, then electrical connection to DRAM cells is achieved, but routing becomes complex and congested in 3D architectures
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by vertically stacking control logic circuitry over the memory array. This vertical dimension allows control signals to be delivered through word lines from below while data signals route horizontally through digit lines, eliminating the need for complex congested routing paths in traditional 3D architectures.
Solution Approach 2:
The control logic circuitry is segmented into functionally distinct blocks (sense amplifiers, sub-word line drivers, etc.) that are distributed across multiple regions of the substrate. Each block handles specific signal routing tasks, allowing simplified local connections rather than requiring complex global routing paths through the entire device.
2Device complexity
If control logic circuitry is vertically offset and positioned over the memory array, then routing complexity is reduced, but device layout becomes more complex
Solution Approach 1:
By moving control logic circuitry to a vertical position above the memory array rather than integrating it within the same planar layer, the patent utilizes the third dimension (vertical height) to separate control signal paths from data signal paths. This spatial separation simplifies routing by eliminating conflicts between control and data lines.
Solution Approach 2:
The control logic circuitry is nested in a complementary metal-oxide-semiconductor (CMOS) device assembly that is positioned vertically above the memory array. This nesting allows multiple control functions to be compactly integrated in a small footprint while maintaining simple routing connections to the memory cells below.
Data Source
AI summary
A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.