3D Memory Stack Openings With Sacrificial Layers for Reliability
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Solution Overview
Problem
The integration density of two-dimensional memory devices has reached limitations, prompting the development of three-dimensional memory devices with stacked memory cells, but existing manufacturing methods struggle to enhance operational reliability and structural stability.
Innovation Solution
A semiconductor device with a stacked structure of alternating conductive and insulating layers, including word lines, select lines, data storage patterns, and channel layers, is manufactured using a method involving sacrificial layers, etching, and the formation of conductive patterns and isolation insulating patterns to ensure electrical coupling and improved structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory devices are used to achieve simple manufacturing, then manufacturing ease is improved, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional memory device architecture to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, while the manufacturing process maintains relative simplicity through standardized layer formation techniques applied repeatedly across stacks.
2Quantity of substance
If three-dimensional memory devices with stacked memory cells are implemented to increase integration density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into modular stages: forming sacrificial layers in a first pattern, creating openings, filling with data storage patterns, removing sacrificial layers, and repeating the process with a second pattern for additional memory cells. This segmentation allows complex three-dimensional structures to be built through systematic repetition of simpler sub-steps, making the overall manufacturing process more manageable and controllable.
Solution Approach 2:
Sacrificial layers are formed in advance before the final memory cell structure is complete. These preliminary sacrificial structures serve as placeholders that guide subsequent manufacturing steps, such as defining opening locations and protecting underlying layers during etching. The sacrificial layers are removed only after they have fulfilled their temporary structural and protective functions.
3Ease of manufacture
If existing manufacturing methods are used for three-dimensional memory devices, then manufacturing process is maintained, but operational reliability is insufficient
Solution Approach 1:
Sacrificial layers serve as intermediary structures during manufacturing. These temporary layers mediate between the manufacturing process requirements and the final device structure, providing mechanical support, defining precise opening locations, and protecting sensitive underlying layers during etching operations. The intermediary sacrificial layers are removed after completing their mediating function, leaving the reliable final structure.
Solution Approach 2:
The manufacturing method incorporates protective measures in advance by forming sacrificial layers that cushion and protect the underlying stacked structure during subsequent processing steps. These sacrificial layers absorb mechanical stress and prevent damage to the delicate memory cell structures during opening formation and material deposition, thereby ensuring operational reliability of the final device.
Data Source
AI summary
A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.