3D Memory Cell Fabrication Using a Sacrificial Pad Etch Stop
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Solution Overview
Problem
The challenge in semiconductor technology is to increase memory cell density while reducing parasitic capacitance, which is hindered by structural limitations in miniaturized memory cells.
Innovation Solution
A semiconductor device is fabricated using a sacrificial pad with auxiliary lines and etch target layers, allowing for the formation of slits and isolation trenches, which enables the vertical stacking of memory cells and reduces parasitic capacitance by using a sacrificial pad as an etch stopper and discharge path during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase net die, then memory cell density increases, but parasitic capacitance increases and structural limitations arise
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Memory cells are stacked in the vertical direction (third direction) using through-silicon vias and interlayer dielectric structures, enabling increased memory cell density without reducing individual cell size. This dimensional change allows simultaneous achievement of high density and low parasitic capacitance by maintaining adequate cell area while utilizing vertical space.
Solution Approach 2:
The memory device is segmented into multiple stacked layers with individual memory cells arranged in three dimensions. Each memory cell is divided into distinct functional regions (word line, bit line, select transistor, capacitor) that are vertically stacked and electrically connected through vias. This segmentation enables independent optimization of each cell component while achieving high overall density.
2Area of stationary object
If memory cell size is reduced, then net die increases, but manufacturing precision requirements increase
Solution Approach 1:
A sacrificial pad structure is introduced as an intermediary element during the fabrication process. This sacrificial pad serves as an etch stop layer that prevents over-etching and damage to underlying structures. The sacrificial pad is selectively removed after forming the desired three-dimensional memory cell structures, enabling precise control of etching depth and protecting critical components from damage during manufacturing.
Solution Approach 2:
The sacrificial pad is formed in advance before the main etching processes. This preliminary structure provides a protective barrier and depth reference during subsequent etching steps, allowing for precise formation of through-silicon vias and isolation trenches without risking damage to the memory cell structures that will be formed later.
3Productivity
If three-dimensional memory cells are implemented, then memory cell density increases, but device complexity increases
Solution Approach 1:
The sacrificial pad structure serves multiple functions simultaneously: it acts as an etch stop layer to prevent over-etching, provides a depth reference for etching processes, protects underlying structures from damage, and serves as a template for forming the three-dimensional memory cell structures. This multi-functionality reduces the need for additional separate structures, thereby managing device complexity while enabling three-dimensional integration.
4Productivity
If etching is performed to form three-dimensional structures, then memory cell density increases, but arcing occurs during etching
Solution Approach 1:
The sacrificial pad acts as an intermediary protective layer during etching processes. It serves as an etch stop that prevents plasma arcing from reaching and damaging the memory cell structures. The sacrificial pad absorbs the arcing energy and can be selectively removed afterward, ensuring that the main memory cell structures remain intact and functional.
Solution Approach 2:
The sacrificial pad is positioned beforehand to cushion and protect the underlying memory cell structures during etching. This protective barrier prevents direct exposure of critical structures to plasma arcing, thereby maintaining etching reliability and preventing damage to the three-dimensional memory cell structures being formed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases memory cell density and reduces parasitic capacitance, improving the reliability and efficiency of semiconductor devices by allowing for the vertical stacking of memory cells and preventing arcing during etching.
Implementation Method 1
forming a plurality of openings by etching the etch-target layer and stopping the etching at the sacrificial pad
Implementation Method 2
forming a pad-type recess by removing the sacrificial pad through the isolation trench
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a sacrificial pad including a plurality of line portions and a plurality of auxiliary lines over a lower structure; forming an etch target layer over the sacrificial pad; forming a plurality of openings by etching the etch-target layer and stopping the etching at the sacrificial pad; forming a pillar filling the openings; forming an isolation trench by etching the etch-target layer and stopping the etching at the sacrificial pad; and forming a pad-type recess by removing the sacrificial pad through the isolation trench.