3D Memory Stair Formation Using Dual-Selectivity Sacrificial Layers
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Solution Overview
Problem
The challenge in forming 3D memory devices is the difficulty in controlling the etch process for sacrificial layers, leading to voids and reduced conductive layer thickness, which increases resistance and impairs device performance.
Innovation Solution
A method involving a sacrificial layer with sub-layers of different etch selectivities is used, where a higher etch rate sub-layer is in contact with the stairs and a lower etch rate sub-layer is on top, allowing for controlled etching through a two-step process to prevent void formation and ensure adequate conductive layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer sacrificial material is used, then the manufacturing process is simpler, but the etching control is poor leading to voids and reduced conductive layer thickness
Solution Approach 1:
The sacrificial material layer is divided into multiple sub-layers with different etch selectivities. The first sub-layer has a higher etch rate than the second sub-layer, allowing differential etching control. This segmentation enables precise control over the etching process while maintaining adequate conductive layer thickness and preventing void formation.
2Productivity
If aggressive etching is used to remove sacrificial material, then the etching speed is faster, but voids form and conductive layer thickness is reduced
Solution Approach 1:
The etch selectivity parameter is changed across different sub-layers of the sacrificial material. The first sub-layer has a higher etch rate parameter, allowing faster initial etching, while the second sub-layer has a lower etch rate parameter that prevents over-etching and void formation. This parameter variation enables both high productivity and precise thickness control.
3Object-generated harmful factors
If the sacrificial layer is completely removed, then the structure is cleaner, but the conductive layer thickness becomes insufficient and resistance increases
Solution Approach 1:
The multi-layer sacrificial structure is designed in advance with different etch rates, where the second sub-layer acts as a protective layer that prevents complete removal of the sacrificial material. This preliminary action ensures that adequate sacrificial material remains to support the conductive layer formation, maintaining sufficient thickness and low resistance while still removing harmful residues through controlled differential etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents voids in the conductive layers, maintaining their thickness and reducing resistance, thereby enhancing the performance of 3D memory devices.
Implementation Method 1
partially removing the first portion of the layer of sacrificial material using an anisotropic etching process
Implementation Method 2
removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process
Data Source
AI summary
The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.