3D Memory Scribe Lane Insulation to Prevent Warpage and Cracks
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Solution Overview
Problem
There is a need for semiconductor memory devices with improved electrical characteristics and reliability, particularly in increasing data storage capacity through three-dimensional arrangements of memory cells, while addressing manufacturing complexities such as warpage and crack prevention.
Innovation Solution
Concurrent formation of holes in the chip region (channel and word line contact holes) and trenches in the scribe lane region, using a method that includes alternately stacking mold and sacrificial layers, forming scribe lane trenches with insulating layers, and providing insulative supports around word line contacts to enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional arrangement of memory cells is implemented to increase data storage capacity, then storage capacity is improved, but manufacturing complexity and reliability risks (warpage and cracks) increase
Solution Approach 1:
The substrate is divided into chip regions and scribe lane regions, with further segmentation into cell array regions and extended regions. This segmentation allows independent optimization of each region, enabling the three-dimensional memory structure to be implemented in chip regions while maintaining structural integrity through properly designed scribe lane regions that prevent warpage and cracks during manufacturing and separation processes
Solution Approach 2:
Mold insulating layers are formed in advance to create a mold structure that defines the three-dimensional arrangement of memory cells. The mold structure is prepared before forming channels and gate electrodes, allowing precise control of the vertical stacking geometry. This preliminary action ensures that the complex three-dimensional structure can be manufactured with high precision, reducing defects and improving reliability
2Quantity of substance
If three-dimensional arrangement of memory cells is implemented to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The mold insulating layers serve multiple functions: they define the geometry of the three-dimensional memory structure, act as spacers during fabrication, and provide structural support throughout the manufacturing process. This multi-functionality reduces the need for additional specialized components, simplifying the overall device architecture while enabling high-capacity three-dimensional storage
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells by introducing mold insulating layers that define vertical channels and alternating gate electrodes. This dimensional change increases storage capacity by utilizing the vertical space above each bit line contact, effectively multiplying the number of storage locations per unit area without proportionally increasing manufacturing complexity
3Ease of manufacture
If conventional manufacturing process is used for three-dimensional memory structure, then manufacturing simplicity is maintained, but warpage and cracks occur reducing reliability
Solution Approach 1:
Different regions of the substrate are given different structures and properties: chip regions contain the active three-dimensional memory cells with vertical channels and gate electrodes, while scribe lane regions contain only mold insulating layers and filling insulating layers without channels. This local differentiation allows the memory regions to achieve high storage capacity while the scribe lane regions maintain structural integrity and prevent warpage during manufacturing and dicing processes
Solution Approach 2:
The scribe lane region is designed with a specific structure including mold insulating layers and filling insulating layers that act as a cushioning structure. This structure compensates for stress and prevents warpage and cracks from propagating into the chip regions during manufacturing processes such as deposition, etching, and dicing. The cushioning effect is built into the design before manufacturing occurs, proactively preventing reliability issues
Data Source
AI summary
A method of manufacturing a semiconductor memory device with improved electrical characteristics and reliability includes providing a substrate including a first chip region, and a scribe lane region surrounding the first chip region, providing a mold including a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked on the substrate in a first direction perpendicular to the substrate, providing a channel extending through the mold in the first direction, and providing a plurality of word line contacts extending through at least a portion of the mold in the first direction, in which the scribe lane region includes a scribe lane trench in the mold, a first insulating layer covering a bottom surface and a sidewall of the scribe lane trench, and a second insulating layer on the first insulating layer and filling the scribe lane trench, in which the substrate includes chip regions other than the first chip region and the method further comprises separating along the scribe lane region the first chip region from the other chip regions.