3D Memory Sealing Structure for Scribing Stress Absorption
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Solution Overview
Problem
The challenge in semiconductor technology is the increasing stress during the scribing process of 3D memory devices, which leads to defects and reduced production yield due to the transmission of stress from the scribing edge to the chip areas, making it difficult to scale down planar memory cells effectively.
Innovation Solution
A two-stage or multiple-stage stress absorption process is implemented using protection structures and contacts in the sealing region to absorb and redirect stress away from the chip region, comprising first and second protection structures and contacts that are strategically positioned to manage stress effectively during the scribing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then storage density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertical channel structures. By forming memory holes extending vertically through the substrate and creating vertical channels within these holes, the invention achieves higher storage density without proportionally increasing manufacturing complexity, as the vertical dimension provides additional scaling space beyond the limits of planar scaling.
2Quantity of substance
If 3D memory architecture is implemented to address density limitations, then storage density increases, but stress during scribing process increases leading to defects
Solution Approach 1:
The patent introduces a stress absorption layer positioned between the memory structure and the substrate surface. This intermediary layer absorbs and redistributes stress generated during the scribing process, preventing stress transmission to the vertical channel structures and memory holes, thereby reducing defects while maintaining the high-density 3D architecture.
Solution Approach 2:
The stress absorption layer is formed in advance before the scribing process occurs. This pre-positioned cushioning layer is specifically designed to mitigate the harmful effects of scribing-induced stress, protecting the delicate vertical channel structures from damage during subsequent manufacturing steps.
3Length of moving object
If feature sizes of memory cells approach lower limit, then planar scaling reaches upper limit, but manufacturing becomes challenging and costly
Solution Approach 1:
The patent circumvents the limitations of planar scaling by transitioning to vertical channel structures. Instead of continuing to reduce lateral feature sizes to the point of manufacturing difficulty, the invention scales storage capacity by extending channels vertically and increasing the number of memory holes, thereby maintaining manufacturability while achieving higher density.
Data Source
AI summary
Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.