3D Memory Wafer Sealing Structure for Scribing Stress Absorption

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Solution Overview

Problem

The challenge in semiconductor technology is the increasing difficulty and cost of scaling down planar memory cells, which limits memory density, and the stress generated during scribing processes in 3D memory device fabrication leads to product defects.

Innovation Solution

A 3D memory device structure with a two-stage or three-stage stress absorption process using protection structures and contacts to absorb stress, where the first protection structure and contacts in the sealing region absorb initial stress, and the second protection structure and contacts in the chip region absorb remaining stress, reducing defects and improving production yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If planar memory cells are scaled down to increase memory density, then memory density is improved, but manufacturing difficulty and cost increase significantly

Engineering Contradiction:

Improvememory densityVSAvoidmanufacturing difficulty

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertical channel structures. By forming memory holes extending vertically through the substrate and creating vertical channels within these holes, the invention achieves increased memory density without further reducing lateral feature sizes, thereby avoiding the manufacturing difficulties associated with extreme planar scaling.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If scribing processes are used in 3D memory device fabrication, then device separation is achieved, but stress generation leads to product defects

Engineering Contradiction:

Improvedevice separation efficiencyVSAvoidproduct defect rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent forms stress compensation structures (such as sacrificial layers or dummy structures) in the scribing regions before the actual scribing process. These preliminary structures are designed to absorb or compensate for the stress that will be generated during scribing, preventing stress-induced defects in the memory devices while still allowing effective device separation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention converts the harmful stress generated during scribing into a beneficial effect by introducing compensatory stress structures. These structures are specifically designed to counterbalance the scribing-induced stress, transforming what would be a defect-causing phenomenon into a controlled process parameter that can be managed and even utilized for stress management in the overall device structure.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250015015A1Three-dimensional memory devices and fabricating methods thereof

Publication Date: 2025.01.09 YANGTZE MEMORY TECH CO LTD

AI summary

Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.