3D Memory Staircase Contact Layout for Multi-Layer Electrical Connection
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Solution Overview
Problem
The existing fabrication processes for staircase contacts (SCTs) in 3D NAND memory devices face challenges in achieving efficient electrical connections and high-density stacking, limiting the performance and capacity of 3D memory devices.
Innovation Solution
A method involving the formation of a conductor/insulator stack with alternating dielectric and conductive layers, channel hole structures, and a staircase contact (SCT) that extends through the dielectric layers, allowing for electrical connection and improved contact with the second dielectric layer, is developed. This includes forming cavities and filling them with conductive material to create a conductive layer that connects the channel hole structure to the bottom of the SCT opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for staircase contacts, then the process is simpler, but electrical connectivity and density are insufficient
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming first and second cavities at different depths, selectively removing dielectric layers, and depositing conductive materials in stages. This segmentation allows precise control over electrical connectivity at different levels while managing overall process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
The staircase contact structure transitions from conventional planar contacts to a three-dimensional stepped configuration. The SCT extends through multiple dielectric layers with conductive plugs at different depths, creating a vertical dimensionality that enhances electrical connectivity and enables higher density stacking in the 3D memory device.
2Quantity of substance
If 3D NAND memory structure is implemented, then density and capacity increase, but fabrication complexity increases
Solution Approach 1:
The 3D memory structure is fabricated through segmented sequential processes: forming alternating dielectric and conductive layers, creating channel holes, depositing word lines, and forming staircase contacts at different stages. Each segmentation step builds upon the previous layer, enabling high density through vertical stacking while maintaining manageable process complexity through systematic progression.
Solution Approach 2:
Dielectric layers are deposited and patterned in advance before conductive materials are added. The first and second dielectric layers are formed preliminarily to define the staircase contact geometry, and cavities are pre-formed at specific depths. These preliminary actions establish the structural framework that guides subsequent conductive material deposition, simplifying the overall 3D fabrication process.
3Reliability
If staircase contact extends through multiple dielectric layers, then electrical connection improves, but manufacturing precision requirements increase
Solution Approach 1:
The first and second dielectric layers serve as intermediary structures that define and protect the staircase contact geometry. These dielectric layers are deposited with controlled thicknesses and patterns, acting as spacers and masks that automatically establish precise alignment for conductive plugs and word lines. The intermediary dielectric structure eliminates the need for complex direct alignment procedures, improving manufacturing precision while maintaining reliable electrical connections through the multi-layer SCT structure.
Data Source
AI summary
A 3D memory device includes a conductor/insulator stack, a channel hole structure extending through the conductor/insulator stack, and a staircase contact (SCT). The conductor/insulator stack includes a first conductive layer and a first dielectric layer alternatingly stacked. The SCT includes a conductive structure, extends through the first dielectric layer, contacts a second dielectric layer, and is electrically connected to the first conductive layer. The second dielectric layer is parallel to the first conductive layer.